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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by CH3PEPF00000013.mail.protection.outlook.com (10.167.244.118) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9343.0 via Frontend Transport; Tue, 11 Nov 2025 03:41:13 +0000 Received: from epycpwr02.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Mon, 10 Nov 2025 19:41:10 -0800 From: Sivaprasad Tummala To: Dariusz Sosnowski , Viacheslav Ovsiienko , Bing Zhao , Ori Kam , Suanming Mou , Matan Azrad , Alexander Kozyrev CC: , Subject: [PATCH v2] net/mlx5: fix spurious CPU wakeups caused by invalid CQE Date: Tue, 11 Nov 2025 03:40:57 +0000 Message-ID: <20251111034057.3177641-1-sivaprasad.tummala@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251015133957.4094235-1-sivaprasad.tummala@amd.com> References: <20251015133957.4094235-1-sivaprasad.tummala@amd.com> MIME-Version: 1.0 Content-Type: text/plain; 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However, when a CQE contained an invalid opcode(MLX5_CQE_INVALID), ownership bit was not reliable. As a result, the monitor condition could falsely indicate CQE availability and cause the CPU to wake up unnecessarily during low traffic periods. This resulted in spurious wakeups in monitor-wait mode and reduced the expected power savings, as cores exited the sleep state even when no valid CQEs were available. This patch introduces a dedicated callback that skips invalid CQEs and optimizes power efficiency by preventing false wakeups caused by hardware-owned or invalid entries. Fixes: a8f0df6bf98d ("net/mlx5: support power monitoring") Cc: akozyrev@nvidia.com Cc: stable@dpdk.org Signed-off-by: Sivaprasad Tummala v2: - Updated CQE opcode check logic — replaced XOR with comparison - Renamed variable match to sw_owned for clarity - Updated CQE ownership check order --- drivers/net/mlx5/mlx5_rx.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c index 420a03068d..ac663a978e 100644 --- a/drivers/net/mlx5/mlx5_rx.c +++ b/drivers/net/mlx5/mlx5_rx.c @@ -295,6 +295,20 @@ mlx5_monitor_callback(const uint64_t value, return (value & m) == v ? -1 : 0; } +static int +mlx5_monitor_cqe_own_callback(const uint64_t value, + const uint64_t opaque[RTE_POWER_MONITOR_OPAQUE_SZ]) +{ + const uint64_t m = opaque[CLB_MSK_IDX]; + const uint64_t v = opaque[CLB_VAL_IDX]; + const uint64_t sw_owned = ((value & m) == v); + const uint64_t opcode = MLX5_CQE_OPCODE(value); + const uint64_t valid_op = (opcode != MLX5_CQE_INVALID); + + /* ownership bit is not valid for invalid opcode; CQE is HW owned */ + return -(valid_op & sw_owned); +} + int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc) { struct mlx5_rxq_data *rxq = rx_queue; @@ -312,12 +326,13 @@ int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc) pmc->addr = &cqe->validity_iteration_count; pmc->opaque[CLB_VAL_IDX] = vic; pmc->opaque[CLB_MSK_IDX] = MLX5_CQE_VIC_INIT; + pmc->fn = mlx5_monitor_callback; } else { pmc->addr = &cqe->op_own; pmc->opaque[CLB_VAL_IDX] = !!idx; pmc->opaque[CLB_MSK_IDX] = MLX5_CQE_OWNER_MASK; + pmc->fn = mlx5_monitor_cqe_own_callback; } - pmc->fn = mlx5_monitor_callback; pmc->size = sizeof(uint8_t); return 0; } -- 2.43.0