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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CH2PEPF00000146.mail.protection.outlook.com (10.167.244.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9320.13 via Frontend Transport; Wed, 12 Nov 2025 13:02:26 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 12 Nov 2025 05:02:04 -0800 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 12 Nov 2025 05:02:01 -0800 From: Gavin Li To: , , , , , CC: , , , Bing Zhao Subject: [PATCH V2] net/mlx5: fix IPv6 DSCP offset in HWS sync API Date: Wed, 12 Nov 2025 15:01:39 +0200 Message-ID: <20251112130139.194450-1-gavinl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250930072827.9630-1-gavinl@nvidia.com> References: <20250930072827.9630-1-gavinl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000146:EE_|SN7PR12MB8101:EE_ X-MS-Office365-Filtering-Correlation-Id: ef06e9bf-9935-4cbe-35ff-08de21ebba86 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(36860700013)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2025 13:02:26.1988 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ef06e9bf-9935-4cbe-35ff-08de21ebba86 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000146.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8101 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org The RTE action process in synchronous flow API with hardware steering differs from the process in SWS. The bit shift handling for IPv6 DSCP was not handled in HWS, resulting in incorrect data in the field. To resolve this, bit shift handling should be added to HWS. Fixes: ec1e7a5ceb69 ("net/mlx5: update IPv6 traffic class modification") Cc: stable@dpdk.org Signed-off-by: Gavin Li Acked-by: Bing Zhao --- drivers/net/mlx5/mlx5_flow.h | 5 +++++ drivers/net/mlx5/mlx5_flow_dv.c | 6 ------ drivers/net/mlx5/mlx5_flow_hw.c | 5 +++++ 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index e8b298dd1d..fafcdccbed 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -3715,6 +3715,11 @@ void mlx5_indirect_list_handles_release(struct rte_eth_dev *dev); bool mlx5_flow_is_steering_disabled(void); +static inline bool +mlx5_dv_modify_ipv6_traffic_class_supported(struct mlx5_priv *priv) +{ + return priv->sh->phdev->config.ipv6_tc_fallback == MLX5_IPV6_TC_OK; +} #ifdef HAVE_MLX5_HWS_SUPPORT diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 95ca57e8c4..83046418c4 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1638,12 +1638,6 @@ mlx5_modify_flex_item(const struct rte_eth_dev *dev, } } -static inline bool -mlx5_dv_modify_ipv6_traffic_class_supported(struct mlx5_priv *priv) -{ - return priv->sh->phdev->config.ipv6_tc_fallback == MLX5_IPV6_TC_OK; -} - void mlx5_flow_field_id_to_modify_info (const struct rte_flow_field_data *data, diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 208f50fbfd..d3d2272338 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -1629,6 +1629,11 @@ flow_hw_modify_field_compile(struct rte_eth_dev *dev, value = *(const uint8_t *)item.spec << 24; value = rte_cpu_to_be_32(value); item.spec = &value; + } else if (conf->dst.field == RTE_FLOW_FIELD_IPV6_DSCP && + !(mask[0] & MLX5_IPV6_HDR_ECN_MASK) && + mlx5_dv_modify_ipv6_traffic_class_supported(dev->data->dev_private)) { + value = *(const unaligned_uint32_t *)item.spec << MLX5_IPV6_HDR_DSCP_SHIFT; + item.spec = &value; } } else { type = conf->operation == RTE_FLOW_MODIFY_SET ? -- 2.34.1