From: luca.boccassi@gmail.com
To: Dariusz Sosnowski <dsosnowski@nvidia.com>
Cc: Bing Zhao <bingz@nvidia.com>, dpdk stable <stable@dpdk.org>
Subject: patch 'net/mlx5: fix indirect RSS action hash' has been queued to stable release 22.11.11
Date: Wed, 12 Nov 2025 16:52:53 +0000 [thread overview]
Message-ID: <20251112165308.1618107-39-luca.boccassi@gmail.com> (raw)
In-Reply-To: <20251112165308.1618107-1-luca.boccassi@gmail.com>
Hi,
FYI, your patch has been queued to stable release 22.11.11
Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 11/14/25. So please
shout if anyone has objections.
Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.
Queued patches are on a temporary branch at:
https://github.com/bluca/dpdk-stable
This queued commit can be viewed at:
https://github.com/bluca/dpdk-stable/commit/ce7841a57c7a24eafe47d6d0b3c67d9495854a54
Thanks.
Luca Boccassi
---
From ce7841a57c7a24eafe47d6d0b3c67d9495854a54 Mon Sep 17 00:00:00 2001
From: Dariusz Sosnowski <dsosnowski@nvidia.com>
Date: Thu, 30 Oct 2025 18:24:04 +0100
Subject: [PATCH] net/mlx5: fix indirect RSS action hash
[ upstream commit 6b010880a505c5609355180a7f99df940a163385 ]
Whenever indirect RSS flow action is created,
mlx5 PMD creates an hrxq object (abstraction over HW object
used to configure RSS hashing),
for all possible and supported protocols combinations.
For each combination, the hrxq configuration is adjusted
based on RSS hash types provided by the user
(e.g. hash on source L3 address is removed if user passed
RTE_ETH_RSS_L3_SRC_ONLY in hash types).
Function used for adjustment, flow_dv_action_rss_l34_hash_adjust(),
had a bug. If user requested, for example, hashing over both UDP ports
and only IPv6 source address, then RSS hashing was configured
to hash both IPv6 addresses. Adjustment for RTE_ETH_RSS_L3_SRC_ONLY
was skipped.
In HW Steering mode, this resulted in failures to use such indirect
RSS flow action in flow rules created through template flow API.
In this mode, only a single hrxq object is selected during flow rule
creation, based on actual configuration of RSS hash types
in flow action.
Since hrxq was created without applying RTE_ETH_RSS_L3_SRC_ONLY
adjustment and RSS hash types contained RTE_ETH_RSS_L3_SRC_ONLY,
then no matching hrxq could be found, resulting in rule creation failure.
This issue is addressed by the following:
- Missing adjustments are added to flow_dv_action_rss_l34_hash_adjust()
function.
This function is reworked to check each protocol type separately,
instead of using switch case over all combinations.
- Code for setting/looking up hrxq objects based on RSS hash types
is reworked. Separate switch cases for possible combinations in each
function are replaced with a single one.
Additional logging and assertions are added to flag any invalid
or missing combinations.
Beside that, the existing set of protocols combinations set
did not cover RSS hashing only over UDP or TCP ports,
which is a valid configuration.
These combinations are added in this patch
(new elements in mlx5_rss_hash_fields array).
Fixes: 212d17b6a650 ("net/mlx5: fix missing shared RSS hash types")
Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Bing Zhao <bingz@nvidia.com>
---
drivers/net/mlx5/mlx5.h | 2 -
drivers/net/mlx5/mlx5_flow.c | 15 ++
drivers/net/mlx5/mlx5_flow.h | 37 ++-
drivers/net/mlx5/mlx5_flow_dv.c | 410 +++++++++++++++++++-------------
4 files changed, 287 insertions(+), 177 deletions(-)
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 3cae07a6b9..a3b01b3589 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -1658,8 +1658,6 @@ struct mlx5_obj_ops {
void (*lb_dummy_queue_release)(struct rte_eth_dev *dev);
};
-#define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields)
-
enum mlx5_hw_ctrl_flow_type {
MLX5_HW_CTRL_FLOW_TYPE_GENERAL,
MLX5_HW_CTRL_FLOW_TYPE_SQ_MISS_ROOT,
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index b69f578ea4..a35fc93d54 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -33,6 +33,21 @@
#include "mlx5_common_os.h"
#include "rte_pmd_mlx5.h"
+const uint64_t mlx5_rss_hash_fields[] = {
+ [MLX5_RSS_HASH_IDX_IPV4] = MLX5_RSS_HASH_IPV4,
+ [MLX5_RSS_HASH_IDX_IPV4_TCP] = MLX5_RSS_HASH_IPV4_TCP,
+ [MLX5_RSS_HASH_IDX_IPV4_UDP] = MLX5_RSS_HASH_IPV4_UDP,
+ [MLX5_RSS_HASH_IDX_IPV4_ESP] = MLX5_RSS_HASH_IPV4_ESP,
+ [MLX5_RSS_HASH_IDX_IPV6] = MLX5_RSS_HASH_IPV6,
+ [MLX5_RSS_HASH_IDX_IPV6_TCP] = MLX5_RSS_HASH_IPV6_TCP,
+ [MLX5_RSS_HASH_IDX_IPV6_UDP] = MLX5_RSS_HASH_IPV6_UDP,
+ [MLX5_RSS_HASH_IDX_IPV6_ESP] = MLX5_RSS_HASH_IPV6_ESP,
+ [MLX5_RSS_HASH_IDX_TCP] = MLX5_TCP_IBV_RX_HASH,
+ [MLX5_RSS_HASH_IDX_UDP] = MLX5_UDP_IBV_RX_HASH,
+ [MLX5_RSS_HASH_IDX_ESP_SPI] = MLX5_RSS_HASH_ESP_SPI,
+ [MLX5_RSS_HASH_IDX_NONE] = MLX5_RSS_HASH_NONE,
+};
+
/*
* Shared array for quick translation between port_id and vport mask/values
* used for HWS rules.
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index ae6d9d45c2..e5672b41f9 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -1398,20 +1398,31 @@ struct rte_flow_template_table {
#define MLX5_RSS_HASH_NONE 0ULL
-/* array of valid combinations of RX Hash fields for RSS */
-static const uint64_t mlx5_rss_hash_fields[] = {
- MLX5_RSS_HASH_IPV4,
- MLX5_RSS_HASH_IPV4_TCP,
- MLX5_RSS_HASH_IPV4_UDP,
- MLX5_RSS_HASH_IPV4_ESP,
- MLX5_RSS_HASH_IPV6,
- MLX5_RSS_HASH_IPV6_TCP,
- MLX5_RSS_HASH_IPV6_UDP,
- MLX5_RSS_HASH_IPV6_ESP,
- MLX5_RSS_HASH_ESP_SPI,
- MLX5_RSS_HASH_NONE,
+
+/**
+ * Each enum variant corresponds to a single valid protocols combination for hrxq configuration
+ * Each variant serves as an index into #mlx5_rss_hash_fields array containing default
+ * bitmaps of ibv_rx_hash_fields flags for given protocols combination.
+ */
+enum {
+ MLX5_RSS_HASH_IDX_IPV4,
+ MLX5_RSS_HASH_IDX_IPV4_TCP,
+ MLX5_RSS_HASH_IDX_IPV4_UDP,
+ MLX5_RSS_HASH_IDX_IPV4_ESP,
+ MLX5_RSS_HASH_IDX_IPV6,
+ MLX5_RSS_HASH_IDX_IPV6_TCP,
+ MLX5_RSS_HASH_IDX_IPV6_UDP,
+ MLX5_RSS_HASH_IDX_IPV6_ESP,
+ MLX5_RSS_HASH_IDX_TCP,
+ MLX5_RSS_HASH_IDX_UDP,
+ MLX5_RSS_HASH_IDX_ESP_SPI,
+ MLX5_RSS_HASH_IDX_NONE,
+ MLX5_RSS_HASH_IDX_MAX,
};
+/** Array of valid combinations of RX Hash fields for RSS. */
+extern const uint64_t mlx5_rss_hash_fields[];
+
/* Shared RSS action structure */
struct mlx5_shared_action_rss {
ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */
@@ -1420,7 +1431,7 @@ struct mlx5_shared_action_rss {
uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
struct mlx5_ind_table_obj *ind_tbl;
/**< Hash RX queues (hrxq, hrxq_tunnel fields) indirection table. */
- uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
+ uint32_t hrxq[MLX5_RSS_HASH_IDX_MAX];
/**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
rte_spinlock_t action_rss_sl; /**< Shared RSS action spinlock. */
};
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 5b8e022f34..fbe6fdeefb 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -14613,6 +14613,145 @@ flow_dv_translate(struct rte_eth_dev *dev,
return 0;
}
+/*
+ * Protocol selector bitmap
+ * Each flag is used as an indicator that given protocol is specified in given RSS hash fields.
+ */
+#define RX_HASH_SELECTOR_IPV4 RTE_BIT32(0)
+#define RX_HASH_SELECTOR_IPV6 RTE_BIT32(1)
+#define RX_HASH_SELECTOR_UDP RTE_BIT32(2)
+#define RX_HASH_SELECTOR_TCP RTE_BIT32(3)
+#define RX_HASH_SELECTOR_ESP_SPI RTE_BIT32(4)
+#define RX_HASH_SELECTOR_NONE (0)
+
+#define RX_HASH_SELECTOR_IPV4_TCP (RX_HASH_SELECTOR_IPV4 | RX_HASH_SELECTOR_TCP)
+#define RX_HASH_SELECTOR_IPV4_UDP (RX_HASH_SELECTOR_IPV4 | RX_HASH_SELECTOR_UDP)
+#define RX_HASH_SELECTOR_IPV4_ESP (RX_HASH_SELECTOR_IPV4 | RX_HASH_SELECTOR_ESP_SPI)
+
+#define RX_HASH_SELECTOR_IPV6_TCP (RX_HASH_SELECTOR_IPV6 | RX_HASH_SELECTOR_TCP)
+#define RX_HASH_SELECTOR_IPV6_UDP (RX_HASH_SELECTOR_IPV6 | RX_HASH_SELECTOR_UDP)
+#define RX_HASH_SELECTOR_IPV6_ESP (RX_HASH_SELECTOR_IPV6 | RX_HASH_SELECTOR_ESP_SPI)
+
+static bool
+rx_hash_selector_has_valid_l3(const uint32_t selectors)
+{
+ /* In TIR configuration, RSS hashing on both IPv4 and IPv6 is mutually exclusive. */
+ return !((selectors & RX_HASH_SELECTOR_IPV4) && (selectors & RX_HASH_SELECTOR_IPV6));
+}
+
+static bool
+rx_hash_selector_has_valid_l4(const uint32_t selectors)
+{
+ /* In TIR configuration, RSS hashing on both UDP and TCP is mutually exclusive. */
+ return !((selectors & RX_HASH_SELECTOR_UDP) && (selectors & RX_HASH_SELECTOR_TCP));
+}
+
+static bool
+rx_hash_selector_has_valid_esp(const uint32_t selectors)
+{
+ /* In TIR configuration, RSS hashing on ESP and other L4 protocol is mutually exclusive. */
+ if (selectors & RX_HASH_SELECTOR_ESP_SPI)
+ return !((selectors & RX_HASH_SELECTOR_UDP) || (selectors & RX_HASH_SELECTOR_TCP));
+
+ return true;
+}
+
+/**
+ * Calculate protocol combination based on provided RSS hashing fields.
+ *
+ * @param[in] hash_fields
+ * Requested RSS hashing fields specified as a flags bitmap, based on ibv_rx_hash_fields.
+ * @param[out] selectors_out
+ * Calculated protocol combination will be written here.
+ * Result will be a bitmap of RX_HASH_SELECTOR_* flags.
+ *
+ * @return
+ * 0 if conversion is successful and protocol combination written to @p selectors_out.
+ * (-EINVAL) otherwise.
+ */
+static int
+rx_hash_calc_selector(const uint64_t hash_fields, uint32_t *selectors_out)
+{
+ const uint64_t filtered_hf = hash_fields & ~IBV_RX_HASH_INNER;
+ uint32_t selectors = 0;
+
+ if (filtered_hf & MLX5_RSS_HASH_IPV4)
+ selectors |= RX_HASH_SELECTOR_IPV4;
+ if (filtered_hf & MLX5_RSS_HASH_IPV6)
+ selectors |= RX_HASH_SELECTOR_IPV6;
+ if (!rx_hash_selector_has_valid_l3(selectors)) {
+ DRV_LOG(NOTICE, "hrxq hashing on both IPv4 and IPv6 is invalid: "
+ "selectors=0x%" PRIx32, selectors);
+ return -EINVAL;
+ }
+
+ if (filtered_hf & MLX5_UDP_IBV_RX_HASH)
+ selectors |= RX_HASH_SELECTOR_UDP;
+ if (filtered_hf & MLX5_TCP_IBV_RX_HASH)
+ selectors |= RX_HASH_SELECTOR_TCP;
+ if (!rx_hash_selector_has_valid_l4(selectors)) {
+ DRV_LOG(NOTICE, "hrxq hashing on both UDP and TCP is invalid: "
+ "selectors=0x%" PRIx32, selectors);
+ return -EINVAL;
+ }
+
+ if (filtered_hf & MLX5_RSS_HASH_ESP_SPI)
+ selectors |= RX_HASH_SELECTOR_ESP_SPI;
+ if (!rx_hash_selector_has_valid_esp(selectors)) {
+ DRV_LOG(NOTICE, "hrxq hashing on ESP SPI and UDP or TCP is mutually exclusive: "
+ "selectors=0x%" PRIx32, selectors);
+ return -EINVAL;
+ }
+
+ *selectors_out = selectors;
+ return 0;
+}
+
+/**
+ * Calculate the hrxq object index based on protocol combination.
+ *
+ * @param[in] selectors
+ * Protocol combination specified as bitmap of RX_HASH_SELECTOR_* flags.
+ *
+ * @return
+ * Index into hrxq array in #mlx5_shared_action_rss based on ginve protocol combination.
+ * (-EINVAL) if given protocol combination is not supported or is invalid.
+ */
+static int
+get_rss_hash_idx(const uint32_t selectors)
+{
+ switch (selectors) {
+ case RX_HASH_SELECTOR_IPV4:
+ return MLX5_RSS_HASH_IDX_IPV4;
+ case RX_HASH_SELECTOR_IPV4_TCP:
+ return MLX5_RSS_HASH_IDX_IPV4_TCP;
+ case RX_HASH_SELECTOR_IPV4_UDP:
+ return MLX5_RSS_HASH_IDX_IPV4_UDP;
+ case RX_HASH_SELECTOR_IPV4_ESP:
+ return MLX5_RSS_HASH_IDX_IPV4_ESP;
+ case RX_HASH_SELECTOR_IPV6:
+ return MLX5_RSS_HASH_IDX_IPV6;
+ case RX_HASH_SELECTOR_IPV6_TCP:
+ return MLX5_RSS_HASH_IDX_IPV6_TCP;
+ case RX_HASH_SELECTOR_IPV6_UDP:
+ return MLX5_RSS_HASH_IDX_IPV6_UDP;
+ case RX_HASH_SELECTOR_IPV6_ESP:
+ return MLX5_RSS_HASH_IDX_IPV6_ESP;
+ case RX_HASH_SELECTOR_TCP:
+ return MLX5_RSS_HASH_IDX_TCP;
+ case RX_HASH_SELECTOR_UDP:
+ return MLX5_RSS_HASH_IDX_UDP;
+ case RX_HASH_SELECTOR_ESP_SPI:
+ return MLX5_RSS_HASH_IDX_ESP_SPI;
+ case RX_HASH_SELECTOR_NONE:
+ return MLX5_RSS_HASH_IDX_NONE;
+ default:
+ DRV_LOG(ERR, "invalid hrxq hash fields combination: "
+ "selectors=0x%" PRIx32, selectors);
+ return -EINVAL;
+ }
+}
+
/**
* Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
* and tunnel.
@@ -14620,7 +14759,8 @@ flow_dv_translate(struct rte_eth_dev *dev,
* @param[in, out] action
* Shred RSS action holding hash RX queue objects.
* @param[in] hash_fields
- * Defines combination of packet fields to participate in RX hash.
+ * Defines combination of packet fields to participate in RX hash,
+ * specified as a bitmap of #ibv_rx_hash_fields flags.
* @param[in] tunnel
* Tunnel type
* @param[in] hrxq_idx
@@ -14635,65 +14775,26 @@ __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
uint32_t hrxq_idx)
{
uint32_t *hrxqs = action->hrxq;
+ uint32_t selectors = 0;
+ int ret;
- switch (hash_fields & ~IBV_RX_HASH_INNER) {
- case MLX5_RSS_HASH_IPV4:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV4_DST_ONLY:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV4_SRC_ONLY:
- hrxqs[0] = hrxq_idx;
- return 0;
- case MLX5_RSS_HASH_IPV4_TCP:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
- hrxqs[1] = hrxq_idx;
- return 0;
- case MLX5_RSS_HASH_IPV4_UDP:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
- hrxqs[2] = hrxq_idx;
- return 0;
- case MLX5_RSS_HASH_IPV6:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV6_DST_ONLY:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV6_SRC_ONLY:
- hrxqs[3] = hrxq_idx;
- return 0;
- case MLX5_RSS_HASH_IPV6_TCP:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
- hrxqs[4] = hrxq_idx;
- return 0;
- case MLX5_RSS_HASH_IPV6_UDP:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
- hrxqs[5] = hrxq_idx;
- return 0;
- case MLX5_RSS_HASH_NONE:
- hrxqs[6] = hrxq_idx;
- return 0;
- case MLX5_RSS_HASH_IPV4_ESP:
- hrxqs[7] = hrxq_idx;
- return 0;
- case MLX5_RSS_HASH_IPV6_ESP:
- hrxqs[8] = hrxq_idx;
- return 0;
- case MLX5_RSS_HASH_ESP_SPI:
- hrxqs[9] = hrxq_idx;
- return 0;
- default:
- return -1;
- }
+ ret = rx_hash_calc_selector(hash_fields, &selectors);
+ /*
+ * Hash fields passed to this function are constructed internally.
+ * If this fails, then this is a PMD bug.
+ */
+ MLX5_ASSERT(ret == 0);
+
+ ret = get_rss_hash_idx(selectors);
+ /*
+ * Based on above assert, selectors should always yield correct index
+ * in mlx5_rss_hash_fields array.
+ * If this fails, then this is a PMD bug.
+ */
+ MLX5_ASSERT(ret >= 0 && ret < MLX5_RSS_HASH_IDX_MAX);
+ hrxqs[ret] = hrxq_idx;
+
+ return 0;
}
/**
@@ -14705,7 +14806,8 @@ __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
* @param[in] idx
* Shared RSS action ID holding hash RX queue objects.
* @param[in] hash_fields
- * Defines combination of packet fields to participate in RX hash.
+ * Defines combination of packet fields to participate in RX hash,
+ * specified as a bitmap of #ibv_rx_hash_fields flags.
* @param[in] tunnel
* Tunnel type
*
@@ -14720,56 +14822,26 @@ flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
struct mlx5_shared_action_rss *shared_rss =
mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
const uint32_t *hrxqs = shared_rss->hrxq;
+ uint32_t selectors = 0;
+ int ret;
- switch (hash_fields & ~IBV_RX_HASH_INNER) {
- case MLX5_RSS_HASH_IPV4:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV4_DST_ONLY:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV4_SRC_ONLY:
- return hrxqs[0];
- case MLX5_RSS_HASH_IPV4_TCP:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
- return hrxqs[1];
- case MLX5_RSS_HASH_IPV4_UDP:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
- return hrxqs[2];
- case MLX5_RSS_HASH_IPV6:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV6_DST_ONLY:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV6_SRC_ONLY:
- return hrxqs[3];
- case MLX5_RSS_HASH_IPV6_TCP:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
- return hrxqs[4];
- case MLX5_RSS_HASH_IPV6_UDP:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
- return hrxqs[5];
- case MLX5_RSS_HASH_NONE:
- return hrxqs[6];
- case MLX5_RSS_HASH_IPV4_ESP:
- return hrxqs[7];
- case MLX5_RSS_HASH_IPV6_ESP:
- return hrxqs[8];
- case MLX5_RSS_HASH_ESP_SPI:
- return hrxqs[9];
- default:
+ ret = rx_hash_calc_selector(hash_fields, &selectors);
+ if (ret < 0) {
+ DRV_LOG(ERR, "port %u Rx hash selector calculation failed: "
+ "rss_act_idx=%u hash_fields=0x%" PRIx64 " selectors=0x%" PRIx32,
+ dev->data->port_id, idx, hash_fields, selectors);
return 0;
}
+ ret = get_rss_hash_idx(selectors);
+ if (ret < 0) {
+ DRV_LOG(ERR, "port %u failed hrxq index lookup: "
+ "rss_act_idx=%u hash_fields=0x%" PRIx64 " selectors=0x%" PRIx32,
+ dev->data->port_id, idx, hash_fields, selectors);
+ return 0;
+ }
+
+ return hrxqs[ret];
}
/**
@@ -15442,7 +15514,7 @@ flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
*/
static int
__flow_dv_hrxqs_release(struct rte_eth_dev *dev,
- uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
+ uint32_t (*hrxqs)[MLX5_RSS_HASH_IDX_MAX])
{
size_t i;
int remaining = 0;
@@ -15477,6 +15549,62 @@ __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
}
+static inline void
+filter_ipv4_types(uint64_t rss_types, uint64_t *hash_fields)
+{
+ if (rss_types & MLX5_IPV4_LAYER_TYPES) {
+ *hash_fields &= ~MLX5_RSS_HASH_IPV4;
+ if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
+ *hash_fields |= IBV_RX_HASH_DST_IPV4;
+ else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
+ *hash_fields |= IBV_RX_HASH_SRC_IPV4;
+ else
+ *hash_fields |= MLX5_RSS_HASH_IPV4;
+ }
+}
+
+static inline void
+filter_ipv6_types(uint64_t rss_types, uint64_t *hash_fields)
+{
+ if (rss_types & MLX5_IPV6_LAYER_TYPES) {
+ *hash_fields &= ~MLX5_RSS_HASH_IPV6;
+ if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
+ *hash_fields |= IBV_RX_HASH_DST_IPV6;
+ else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
+ *hash_fields |= IBV_RX_HASH_SRC_IPV6;
+ else
+ *hash_fields |= MLX5_RSS_HASH_IPV6;
+ }
+}
+
+static inline void
+filter_udp_types(uint64_t rss_types, uint64_t *hash_fields)
+{
+ if (rss_types & RTE_ETH_RSS_UDP) {
+ *hash_fields &= ~MLX5_UDP_IBV_RX_HASH;
+ if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
+ *hash_fields |= IBV_RX_HASH_DST_PORT_UDP;
+ else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
+ *hash_fields |= IBV_RX_HASH_SRC_PORT_UDP;
+ else
+ *hash_fields |= MLX5_UDP_IBV_RX_HASH;
+ }
+}
+
+static inline void
+filter_tcp_types(uint64_t rss_types, uint64_t *hash_fields)
+{
+ if (rss_types & RTE_ETH_RSS_TCP) {
+ *hash_fields &= ~MLX5_TCP_IBV_RX_HASH;
+ if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
+ *hash_fields |= IBV_RX_HASH_DST_PORT_TCP;
+ else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
+ *hash_fields |= IBV_RX_HASH_SRC_PORT_TCP;
+ else
+ *hash_fields |= MLX5_TCP_IBV_RX_HASH;
+ }
+}
+
/**
* Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
* user input.
@@ -15488,9 +15616,9 @@ __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
* same slot in mlx5_rss_hash_fields.
*
* @param[in] orig_rss_types
- * RSS type as provided in shared RSS action.
+ * RSS type as provided in shared RSS action, specified as a bitmap of RTE_ETH_RSS_* flags.
* @param[in, out] hash_field
- * hash_field variable needed to be adjusted.
+ * hash_field variable needed to be adjusted, specified as a bitmap of #ibv_rx_hash_fields flags.
*
* @return
* void
@@ -15499,60 +15627,18 @@ void
flow_dv_action_rss_l34_hash_adjust(uint64_t orig_rss_types,
uint64_t *hash_field)
{
+ uint64_t hash_field_protos = *hash_field & ~IBV_RX_HASH_INNER;
uint64_t rss_types = rte_eth_rss_hf_refine(orig_rss_types);
- switch (*hash_field & ~IBV_RX_HASH_INNER) {
- case MLX5_RSS_HASH_IPV4:
- if (rss_types & MLX5_IPV4_LAYER_TYPES) {
- *hash_field &= ~MLX5_RSS_HASH_IPV4;
- if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
- *hash_field |= IBV_RX_HASH_DST_IPV4;
- else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
- *hash_field |= IBV_RX_HASH_SRC_IPV4;
- else
- *hash_field |= MLX5_RSS_HASH_IPV4;
- }
- return;
- case MLX5_RSS_HASH_IPV6:
- if (rss_types & MLX5_IPV6_LAYER_TYPES) {
- *hash_field &= ~MLX5_RSS_HASH_IPV6;
- if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
- *hash_field |= IBV_RX_HASH_DST_IPV6;
- else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
- *hash_field |= IBV_RX_HASH_SRC_IPV6;
- else
- *hash_field |= MLX5_RSS_HASH_IPV6;
- }
- return;
- case MLX5_RSS_HASH_IPV4_UDP:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV6_UDP:
- if (rss_types & RTE_ETH_RSS_UDP) {
- *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
- if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
- *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
- else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
- *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
- else
- *hash_field |= MLX5_UDP_IBV_RX_HASH;
- }
- return;
- case MLX5_RSS_HASH_IPV4_TCP:
- /* fall-through. */
- case MLX5_RSS_HASH_IPV6_TCP:
- if (rss_types & RTE_ETH_RSS_TCP) {
- *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
- if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
- *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
- else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
- *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
- else
- *hash_field |= MLX5_TCP_IBV_RX_HASH;
- }
- return;
- default:
- return;
- }
+ if (hash_field_protos & MLX5_RSS_HASH_IPV4)
+ filter_ipv4_types(rss_types, hash_field);
+ else if (hash_field_protos & MLX5_RSS_HASH_IPV6)
+ filter_ipv6_types(rss_types, hash_field);
+
+ if (hash_field_protos & MLX5_UDP_IBV_RX_HASH)
+ filter_udp_types(rss_types, hash_field);
+ else if (hash_field_protos & MLX5_TCP_IBV_RX_HASH)
+ filter_tcp_types(rss_types, hash_field);
}
/**
@@ -15602,7 +15688,7 @@ __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
rss_desc.ind_tbl = shared_rss->ind_tbl;
if (priv->sh->config.dv_flow_en == 2)
rss_desc.hws_flags = MLX5DR_ACTION_FLAG_HWS_RX;
- for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
+ for (i = 0; i < MLX5_RSS_HASH_IDX_MAX; i++) {
struct mlx5_hrxq *hrxq;
uint64_t hash_fields = mlx5_rss_hash_fields[i];
int tunnel = 0;
--
2.47.3
---
Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- - 2025-11-12 16:20:42.440137235 +0000
+++ 0039-net-mlx5-fix-indirect-RSS-action-hash.patch 2025-11-12 16:20:40.991718522 +0000
@@ -1 +1 @@
-From 6b010880a505c5609355180a7f99df940a163385 Mon Sep 17 00:00:00 2001
+From ce7841a57c7a24eafe47d6d0b3c67d9495854a54 Mon Sep 17 00:00:00 2001
@@ -5,0 +6,2 @@
+[ upstream commit 6b010880a505c5609355180a7f99df940a163385 ]
+
@@ -49 +50,0 @@
-Cc: stable@dpdk.org
@@ -61 +62 @@
-index 203cf00596..7e4bfacd11 100644
+index 3cae07a6b9..a3b01b3589 100644
@@ -64 +65 @@
-@@ -1842,8 +1842,6 @@ struct mlx5_obj_ops {
+@@ -1658,8 +1658,6 @@ struct mlx5_obj_ops {
@@ -70,3 +71,3 @@
- enum mlx5_ctrl_flow_type {
- MLX5_CTRL_FLOW_TYPE_GENERAL,
- MLX5_CTRL_FLOW_TYPE_SQ_MISS_ROOT,
+ enum mlx5_hw_ctrl_flow_type {
+ MLX5_HW_CTRL_FLOW_TYPE_GENERAL,
+ MLX5_HW_CTRL_FLOW_TYPE_SQ_MISS_ROOT,
@@ -74 +75 @@
-index 098ef9d034..ed67a90a22 100644
+index b69f578ea4..a35fc93d54 100644
@@ -77 +78 @@
-@@ -34,6 +34,21 @@
+@@ -33,6 +33,21 @@
@@ -100 +101 @@
-index ef743fc3cb..2de0f35815 100644
+index ae6d9d45c2..e5672b41f9 100644
@@ -103,3 +104,3 @@
-@@ -1897,20 +1897,31 @@ flow_hw_get_reg_id_from_ctx(void *dr_ctx, enum rte_flow_item_type type,
- (((func) == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) || \
- ((func) == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ_SORT))
+@@ -1398,20 +1398,31 @@ struct rte_flow_template_table {
+ #define MLX5_RSS_HASH_NONE 0ULL
+
@@ -147 +148 @@
-@@ -1919,7 +1930,7 @@ struct mlx5_shared_action_rss {
+@@ -1420,7 +1431,7 @@ struct mlx5_shared_action_rss {
@@ -157 +158 @@
-index 1564bd7cbe..f765f94116 100644
+index 5b8e022f34..fbe6fdeefb 100644
@@ -160 +161 @@
-@@ -15788,6 +15788,145 @@ flow_dv_translate(struct rte_eth_dev *dev,
+@@ -14613,6 +14613,145 @@ flow_dv_translate(struct rte_eth_dev *dev,
@@ -306 +307 @@
-@@ -15795,7 +15934,8 @@ flow_dv_translate(struct rte_eth_dev *dev,
+@@ -14620,7 +14759,8 @@ flow_dv_translate(struct rte_eth_dev *dev,
@@ -316 +317 @@
-@@ -15810,65 +15950,26 @@ __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
+@@ -14635,65 +14775,26 @@ __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
@@ -401 +402 @@
-@@ -15880,7 +15981,8 @@ __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
+@@ -14705,7 +14806,8 @@ __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
@@ -411 +412 @@
-@@ -15895,56 +15997,26 @@ flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
+@@ -14720,56 +14822,26 @@ flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
@@ -484 +485 @@
-@@ -16634,7 +16706,7 @@ flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
+@@ -15442,7 +15514,7 @@ flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
@@ -493 +494 @@
-@@ -16669,6 +16741,62 @@ __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
+@@ -15477,6 +15549,62 @@ __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
@@ -556 +557 @@
-@@ -16680,9 +16808,9 @@ __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
+@@ -15488,9 +15616,9 @@ __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
@@ -568 +569 @@
-@@ -16691,60 +16819,18 @@ void
+@@ -15499,60 +15627,18 @@ void
@@ -639 +640 @@
-@@ -16796,7 +16882,7 @@ __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
+@@ -15602,7 +15688,7 @@ __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
next prev parent reply other threads:[~2025-11-12 16:55 UTC|newest]
Thread overview: 130+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-27 16:18 patch 'net/gve: allocate Rx QPL pages using malloc' " luca.boccassi
2025-10-27 16:18 ` patch 'eal: fix plugin dir walk' " luca.boccassi
2025-10-27 16:18 ` patch 'cmdline: fix port list parsing' " luca.boccassi
2025-10-27 16:18 ` patch 'cmdline: fix highest bit " luca.boccassi
2025-10-27 16:18 ` patch 'tailq: fix lookup macro' " luca.boccassi
2025-10-27 16:18 ` patch 'hash: fix unaligned access in predictable RSS' " luca.boccassi
2025-10-27 16:18 ` patch 'graph: fix unaligned access in stats' " luca.boccassi
2025-10-27 16:18 ` patch 'eventdev: fix listing timer adapters with telemetry' " luca.boccassi
2025-10-27 16:18 ` patch 'cfgfile: fix section count with no name' " luca.boccassi
2025-10-27 16:18 ` patch 'net/vmxnet3: fix mapping of mempools to queues' " luca.boccassi
2025-10-27 16:18 ` patch 'app/testpmd: increase size of set cores list command' " luca.boccassi
2025-10-27 16:18 ` patch 'net/dpaa2: fix shaper rate' " luca.boccassi
2025-10-27 16:18 ` patch 'app/testpmd: monitor state of primary process' " luca.boccassi
2025-10-27 16:18 ` patch 'app/testpmd: fix conntrack action query' " luca.boccassi
2025-10-27 16:18 ` patch 'doc: add conntrack state inspect command to testpmd guide' " luca.boccassi
2025-10-27 16:18 ` patch 'app/testpmd: validate DSCP and VLAN for meter creation' " luca.boccassi
2025-10-27 16:18 ` patch 'net/mlx5: fix min and max MTU reporting' " luca.boccassi
2025-10-27 16:18 ` patch 'net/mlx5: fix unsupported flow rule port action' " luca.boccassi
2025-10-27 16:18 ` patch 'net/mlx5: fix non-template age rules flush' " luca.boccassi
2025-10-27 16:18 ` patch 'net/mlx5: fix connection tracking state item validation' " luca.boccassi
2025-10-27 16:18 ` patch 'net/mlx5: fix indirect flow age action handling' " luca.boccassi
2025-10-27 16:19 ` patch 'net/mlx5: fix Direct Verbs counter offset detection' " luca.boccassi
2025-10-27 16:19 ` patch 'net/mlx5: fix interface name parameter definition' " luca.boccassi
2025-10-27 16:19 ` patch 'net/intel: fix assumption about tag placement order' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ice/base: fix adding special words' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ice/base: fix memory leak in HW profile handling' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ice/base: fix memory leak in recipe " luca.boccassi
2025-10-27 16:19 ` patch 'eal: fix DMA mask validation with IOVA mode option' " luca.boccassi
2025-10-27 16:19 ` patch 'eal: fix MP socket cleanup' " luca.boccassi
2025-10-27 16:19 ` patch 'crypto/ipsec_mb: fix QP release in secondary' " luca.boccassi
2025-10-27 16:19 ` patch 'efd: fix AVX2 support' " luca.boccassi
2025-10-27 16:19 ` patch 'common/cnxk: fix async event handling' " luca.boccassi
2025-10-27 16:19 ` patch 'doc: fix feature list of ice driver' " luca.boccassi
2025-10-27 16:19 ` patch 'doc: fix feature list of iavf " luca.boccassi
2025-10-27 16:19 ` patch 'baseband/acc: fix exported header' " luca.boccassi
2025-10-27 16:19 ` patch 'gpudev: fix driver header for Windows' " luca.boccassi
2025-10-27 16:19 ` patch 'drivers: fix some exported headers' " luca.boccassi
2025-10-27 16:19 ` patch 'test/debug: fix crash with mlx5 devices' " luca.boccassi
2025-10-27 16:19 ` patch 'bus/pci: fix build with MinGW 13' " luca.boccassi
2025-10-27 16:19 ` patch 'net/mlx5: " luca.boccassi
2025-10-27 16:19 ` patch 'dma/hisilicon: fix stop with pending transfers' " luca.boccassi
2025-10-27 16:19 ` patch 'test/dma: fix failure condition' " luca.boccassi
2025-10-27 16:19 ` patch 'fib6: fix tbl8 allocation check logic' " luca.boccassi
2025-10-27 16:19 ` patch 'vhost: fix double fetch when dequeue offloading' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ice/base: fix integer overflow on NVM init' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ice: fix initialization with 8 ports' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ice: remove indirection for FDIR filters' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ice: fix memory leak in raw pattern parse' " luca.boccassi
2025-10-27 16:19 ` patch 'net/i40e: fix symmetric Toeplitz hashing for SCTP' " luca.boccassi
2025-10-27 16:19 ` patch 'net/mlx5: fix multicast' " luca.boccassi
2025-10-27 16:19 ` patch 'net/mlx5: fix MTU initialization' " luca.boccassi
2025-10-27 16:19 ` patch 'net/mlx5: fix leak of flow indexed pools' " luca.boccassi
2025-10-27 16:19 ` patch 'net/hns3: fix inconsistent lock' " luca.boccassi
2025-10-27 16:19 ` patch 'net/hns3: fix VLAN resources freeing' " luca.boccassi
2025-10-27 16:19 ` patch 'net/af_packet: fix crash in secondary process' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ark: remove double mbuf free' " luca.boccassi
2025-10-27 16:19 ` patch 'net/hns3: fix VLAN tag loss for short tunnel frame' " luca.boccassi
2025-10-27 16:19 ` patch 'ethdev: fix VLAN filter parameter description' " luca.boccassi
2025-10-27 16:19 ` patch 'net/enetfec: fix file descriptor leak on read error' " luca.boccassi
2025-10-27 16:19 ` patch 'net/enetfec: fix out-of-bounds access in UIO mapping' " luca.boccassi
2025-10-27 16:19 ` patch 'net/enetfec: fix buffer descriptor size configuration' " luca.boccassi
2025-10-27 16:19 ` patch 'net/enetfec: fix Tx queue free' " luca.boccassi
2025-10-27 16:19 ` patch 'net/enetfec: fix checksum flag handling and error return' " luca.boccassi
2025-10-27 16:19 ` patch 'net/enetfec: reject multi-queue configuration' " luca.boccassi
2025-10-27 16:19 ` patch 'net/enetfec: fix memory leak in Rx buffer cleanup' " luca.boccassi
2025-10-27 16:19 ` patch 'net/enetfec: reject Tx deferred queue' " luca.boccassi
2025-10-27 16:19 ` patch 'net/tap: fix interrupt callback crash after failed start' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ena: fix PCI BAR mapping on 64K page size' " luca.boccassi
2025-10-27 16:19 ` patch 'net/ena/base: fix unsafe memcpy on invalid memory' " luca.boccassi
2025-10-27 16:19 ` patch 'net/dpaa2: fix uninitialized variable' " luca.boccassi
2025-10-27 16:19 ` patch 'net/dpaa2: fix L3/L4 checksum results' " luca.boccassi
2025-10-27 16:19 ` patch 'net/dpaa2: receive packets with additional parse errors' " luca.boccassi
2025-10-27 16:19 ` patch 'crypto/qat: fix source buffer alignment' " luca.boccassi
2025-10-27 16:19 ` patch 'crypto/cnxk: refactor RSA verification' " luca.boccassi
2025-10-27 16:19 ` patch 'test/crypto: fix mbuf handling' " luca.boccassi
2025-10-27 16:19 ` patch 'app/crypto-perf: fix plaintext size exceeds buffer size' " luca.boccassi
2025-10-27 16:19 ` patch 'test/crypto: fix vector initialization' " luca.boccassi
2025-10-27 16:19 ` patch 'crypto/virtio: fix cookies leak' " luca.boccassi
2025-10-27 16:19 ` patch 'sched: fix WRR parameter data type' " luca.boccassi
2025-11-12 16:52 ` patch 'test/hash: check memory allocation' " luca.boccassi
2025-11-12 16:52 ` patch 'dmadev: fix debug build with tracepoints' " luca.boccassi
2025-11-12 16:52 ` patch 'buildtools/pmdinfogen: fix warning with python 3.14' " luca.boccassi
2025-11-12 16:52 ` patch 'net/iavf: fix build with clang 21' " luca.boccassi
2025-11-12 16:52 ` patch 'eventdev/crypto: " luca.boccassi
2025-11-12 16:52 ` patch 'rawdev: " luca.boccassi
2025-11-12 16:52 ` patch 'vdpa/mlx5: remove unused constant' " luca.boccassi
2025-11-12 16:52 ` patch 'crypto/mlx5: remove unused constants' " luca.boccassi
2025-11-12 16:52 ` patch 'regex/mlx5: remove useless " luca.boccassi
2025-11-12 16:52 ` patch 'common/mlx5: " luca.boccassi
2025-11-12 16:52 ` patch 'net/mlx5: " luca.boccassi
2025-11-12 16:52 ` patch 'net/mlx5: remove unused macros' " luca.boccassi
2025-11-12 16:52 ` patch 'doc: fix NVIDIA bifurcated driver presentation link' " luca.boccassi
2025-11-12 16:52 ` patch 'vfio: fix custom containers in multiprocess' " luca.boccassi
2025-11-12 16:52 ` patch 'net/vmxnet3: disable RSS for single queue for ESX8.0+' " luca.boccassi
2025-11-12 16:52 ` patch 'net/dpaa: fix resource leak' " luca.boccassi
2025-11-12 16:52 ` patch 'net/txgbe: reduce memory size of ring descriptors' " luca.boccassi
2025-11-12 16:52 ` patch 'net/ngbe: " luca.boccassi
2025-11-12 16:52 ` patch 'net/txgbe: fix VF Rx buffer size in config register' " luca.boccassi
2025-11-12 16:52 ` patch 'net/txgbe: add device arguments for FDIR' " luca.boccassi
2025-11-12 16:52 ` patch 'net/txgbe: fix maximum number of FDIR filters' " luca.boccassi
2025-11-12 16:52 ` patch 'net/txgbe: fix FDIR mode clearing' " luca.boccassi
2025-11-12 16:52 ` patch 'net/txgbe: fix FDIR drop action for L4 match packets' " luca.boccassi
2025-11-12 16:52 ` patch 'net/txgbe: fix FDIR filter for SCTP tunnel' " luca.boccassi
2025-11-12 16:52 ` patch 'net/txgbe: filter FDIR match flex bytes for " luca.boccassi
2025-11-12 16:52 ` patch 'net/txgbe: fix FDIR rule raw relative for L3 packets' " luca.boccassi
2025-11-12 16:52 ` patch 'net/txgbe: fix FDIR input mask' " luca.boccassi
2025-11-12 16:52 ` patch 'net/txgbe: switch to FDIR when ntuple filter is full' " luca.boccassi
2025-11-12 16:52 ` patch 'net/txgbe: remove unsupported flow action mark' " luca.boccassi
2025-11-12 16:52 ` patch 'net/bonding: fix MAC address propagation in 802.3ad mode' " luca.boccassi
2025-11-12 16:52 ` patch 'app/testpmd: fix DCB Tx port' " luca.boccassi
2025-11-12 16:52 ` patch 'app/testpmd: fix DCB Rx queues' " luca.boccassi
2025-11-12 16:52 ` patch 'net/e1000/base: fix crash on init with GCC 13' " luca.boccassi
2025-11-12 16:52 ` patch 'net/fm10k: fix build with GCC 16' " luca.boccassi
2025-11-12 16:52 ` patch 'net/mlx4: fix unnecessary comma' " luca.boccassi
2025-11-12 16:52 ` patch 'net/mlx5: fix unnecessary commas' " luca.boccassi
2025-11-12 16:52 ` patch 'net/mlx5: fix multi-process Tx default rules' " luca.boccassi
2025-11-12 16:52 ` patch 'net/mlx5: store MTU at Rx queue allocation time' " luca.boccassi
2025-11-12 16:52 ` luca.boccassi [this message]
2025-11-12 16:52 ` patch 'net/mlx5: fix indirect meter index leak' " luca.boccassi
2025-11-12 16:52 ` patch 'net/mlx5: fix error reporting on masked indirect actions' " luca.boccassi
2025-11-12 16:52 ` patch 'net: fix L2 length for GRE packets' " luca.boccassi
2025-11-12 16:52 ` patch 'graph: fix updating edge with active graph' " luca.boccassi
2025-11-12 16:52 ` patch 'app/pdump: remove hard-coded memory channels' " luca.boccassi
2025-11-12 16:52 ` patch 'pdump: handle primary process exit' " luca.boccassi
2025-11-12 16:53 ` patch 'examples/l3fwd-power: fix telemetry command registration' " luca.boccassi
2025-11-12 16:53 ` patch 'lib: fix backticks matching in Doxygen comments' " luca.boccassi
2025-11-12 16:53 ` patch 'ring: establish safe partial order in default mode' " luca.boccassi
2025-11-12 19:12 ` Wathsala Vithanage
2025-11-12 21:12 ` Luca Boccassi
2025-11-12 16:53 ` patch 'doc: add device arguments in txgbe guide' " luca.boccassi
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