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Sun, 21 Dec 2025 06:59:51 -0800 From: Shani Peretz To: Joshua Washington CC: Praveen Kaligineedi , dpdk stable Subject: patch 'net/gve: fix disabling interrupts on DQ' has been queued to stable release 23.11.6 Date: Sun, 21 Dec 2025 16:56:04 +0200 Message-ID: <20251221145746.763179-16-shperetz@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251221145746.763179-1-shperetz@nvidia.com> References: <20251221145746.763179-1-shperetz@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B36F:EE_|SN7PR12MB8792:EE_ X-MS-Office365-Filtering-Correlation-Id: 4588abbe-9ac9-4a51-eb57-08de40a1a239 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|376014|1800799024|36860700013|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?BvFJ9fG3RSuk/2Ol7cbrupRBF2HkV+Dv8JYdF9zFQGi5dPTIBwoO66xxg+Rv?= =?us-ascii?Q?WBBKncXbY5x341+1zn/1F1x3zYmuxPo+nCdg/+ecXCddUq5DTG+XuM0QhXIF?= =?us-ascii?Q?/R1w3OMWrbNrQdQ804fidO678KZov3LB6j75JEJz1KX+RMZpE1D/DvaKJHGz?= =?us-ascii?Q?07OUwRMscPNqcp1VI2GShOERwIFVJjhrQvPrUFck4zsbQeOWj4DxmpTi+Bzu?= =?us-ascii?Q?9GBmqd3FOvUH5dYlWpU2U14e6aUR/QkSsPt8ZxxGzoNsZ/tz3V82aQgJy1qY?= =?us-ascii?Q?WtcrprBrvQv2Pwd0pmSi5aqSwU40pYwNZ4h4r6kqXj2MtmL4Cx7lBsHJiVWr?= =?us-ascii?Q?Pg7ApmDyX1wL9v7nuLNpy/7FTHT1tnqbzWYXWn437QwC6g9zJWYsFvCGrcME?= =?us-ascii?Q?IijrrfItlsi3TKjmmSKHcjjcEcuPi2SnIpfRRZr51NUnW76gB5WzINtFv7RF?= =?us-ascii?Q?rbUEfYibHHHU8AsBlgdVbZXndW17KPIZSHRMUp06c7DDwCIfaGIPKiKar6Ni?= =?us-ascii?Q?U/fl4P9GVU5yYyO3fWtMO/5429BZMMDsHz+ca8wRPFRSRSxcc7jl+leJirAq?= =?us-ascii?Q?te5CX149QNZvwvruVFZtagjmUnlmhbAWdRrb915BAooN4cAEjiPCCm7AC4BE?= =?us-ascii?Q?lsNtAg+Dbdos3nWe1li6rUMP7QURB59LqvBooLFKNpW5xrKd/ZhW3wStSC18?= =?us-ascii?Q?0fiRQcdDUTsmODvE30CCkjnDROA3ZNhCbI4CjQQrcQxnaCe87BaJtNJUyMyt?= =?us-ascii?Q?Mn/LLVli0n75epFcFxSgPsDx5FbV4Xn/fcThDNkMshfELRp9gaU4OFY4TTBe?= =?us-ascii?Q?4gVE/ktpOq8WqNUWyNj/7CCd26k8DsH5EUPPpyhyMI+x+7iMuMPlNboOuIbE?= =?us-ascii?Q?pGi/Ai43lQRsrErGOs8mL4VLW906dtMyEo4jdyjmfaITyn4VmGl7zTUlshmI?= =?us-ascii?Q?YZs/5KvDLp3XLRMnNWac6d9nVB9IBdAdyEeGHvepxDKi758OHCU+3OQw8lfM?= =?us-ascii?Q?NZDkpy3fdlZuApac1MUXKmGEb/AVu+WntrFrR8HuIIOCRaO4CRqJjvcDSCfn?= =?us-ascii?Q?U2Gj5LSi9xKHJPh0xdzMBlwsVn7J7TQhNSGqH97mZBi+T4DL+EQm4IBtevif?= =?us-ascii?Q?h04hiNU2I6twU2EXrzL8rY4iwDBmUb+WZXI3n/z8xeK4i/t/a4LGtw/IcQms?= =?us-ascii?Q?E3euJmL4w2L7FWMuG9fkE4sNsw49zFlmBh9jqBZRckzNKe3KUEDjer/2Jgrx?= =?us-ascii?Q?Lp6pFgqHHais6o0MkIR1HYrjHo5UIG2d+M6kvAkKhiviImHmb1OKBOYXt3tf?= =?us-ascii?Q?PynbzFo3IwgBj9ZDjMw54Ww/E9AP7rclHu+vk/SymvxdjpzESm7whj4w7bCq?= =?us-ascii?Q?QFeW/dtWyDuxiJMBjuWLyANgmEfrqr5MtZCcJmUOlNgGxiV9h+IQ+EO6YUJ/?= =?us-ascii?Q?KWype53Pk+6qwPUfu+HsPKYyAdgpQ2csnFa1yhfim8WE5/CeKM0+riOmcJ4u?= =?us-ascii?Q?4Sk+564u9nL7VoW7Pe5wsCKZNSSsGwSEIK8vx9QOAyRiLy/wH17HCUrBLgvE?= =?us-ascii?Q?eTPYEy3yZkpFKIJlh+utQjOPu1tbvYRRIxRHg60N?= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(376014)(1800799024)(36860700013)(7053199007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Dec 2025 15:00:08.6831 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4588abbe-9ac9-4a51-eb57-08de40a1a239 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B36F.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8792 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 23.11.6 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 12/26/25. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/shanipr/dpdk-stable This queued commit can be viewed at: https://github.com/shanipr/dpdk-stable/commit/777a100ca784394be1a363b3f40c29914e2ab8fb Thanks. Shani --- >From 777a100ca784394be1a363b3f40c29914e2ab8fb Mon Sep 17 00:00:00 2001 From: Joshua Washington Date: Mon, 4 Aug 2025 13:50:24 -0700 Subject: [PATCH] net/gve: fix disabling interrupts on DQ [ upstream commit 8a6418e11a4d9e3554d592b1b3e3957fea8e7cee ] When starting Rx and Tx queues in the DQ queue format, the driver was erroneously writing GVE_IRQ_MASK to the IRQ doorbell. GQ and DQ have different interrupt register layouts, so writing this bit is incorrect. Update the register write to properly enable NO_INT_MODE for DQO. Fixes: b044845bb015 ("net/gve: support queue start/stop") Signed-off-by: Joshua Washington Reviewed-by: Praveen Kaligineedi --- drivers/net/gve/base/gve_desc_dqo.h | 4 ++++ drivers/net/gve/gve_rx_dqo.c | 4 +++- drivers/net/gve/gve_tx_dqo.c | 4 +++- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/net/gve/base/gve_desc_dqo.h b/drivers/net/gve/base/gve_desc_dqo.h index bb4a18d4d1..71d9d60bb9 100644 --- a/drivers/net/gve/base/gve_desc_dqo.h +++ b/drivers/net/gve/base/gve_desc_dqo.h @@ -248,4 +248,8 @@ GVE_CHECK_STRUCT_LEN(32, gve_rx_compl_desc_dqo); */ #define GVE_RX_BUF_THRESH_DQO 32 +/* GVE IRQ */ +#define GVE_NO_INT_MODE_DQO BIT(30) +#define GVE_ITR_NO_UPDATE_DQO (3 << 3) + #endif /* _GVE_DESC_DQO_H_ */ diff --git a/drivers/net/gve/gve_rx_dqo.c b/drivers/net/gve/gve_rx_dqo.c index 3f694a4d9a..bf8b3dbd36 100644 --- a/drivers/net/gve/gve_rx_dqo.c +++ b/drivers/net/gve/gve_rx_dqo.c @@ -355,7 +355,9 @@ gve_rx_queue_start_dqo(struct rte_eth_dev *dev, uint16_t rx_queue_id) rxq->qrx_tail = &hw->db_bar2[rte_be_to_cpu_32(rxq->qres->db_index)]; - rte_write32(rte_cpu_to_be_32(GVE_IRQ_MASK), rxq->ntfy_addr); + rte_write32(rte_cpu_to_le_32(GVE_NO_INT_MODE_DQO | + GVE_ITR_NO_UPDATE_DQO), + rxq->ntfy_addr); ret = gve_rxq_mbufs_alloc_dqo(rxq); if (ret != 0) { diff --git a/drivers/net/gve/gve_tx_dqo.c b/drivers/net/gve/gve_tx_dqo.c index 9550fe58c7..95a02bab17 100644 --- a/drivers/net/gve/gve_tx_dqo.c +++ b/drivers/net/gve/gve_tx_dqo.c @@ -408,7 +408,9 @@ gve_tx_queue_start_dqo(struct rte_eth_dev *dev, uint16_t tx_queue_id) txq->qtx_head = &hw->cnt_array[rte_be_to_cpu_32(txq->qres->counter_index)]; - rte_write32(rte_cpu_to_be_32(GVE_IRQ_MASK), txq->ntfy_addr); + rte_write32(rte_cpu_to_le_32(GVE_NO_INT_MODE_DQO | + GVE_ITR_NO_UPDATE_DQO), + txq->ntfy_addr); dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; -- 2.43.0 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2025-12-21 16:54:18.183464625 +0200 +++ 0016-net-gve-fix-disabling-interrupts-on-DQ.patch 2025-12-21 16:54:16.720046000 +0200 @@ -1 +1 @@ -From 8a6418e11a4d9e3554d592b1b3e3957fea8e7cee Mon Sep 17 00:00:00 2001 +From 777a100ca784394be1a363b3f40c29914e2ab8fb Mon Sep 17 00:00:00 2001 @@ -5,0 +6,2 @@ +[ upstream commit 8a6418e11a4d9e3554d592b1b3e3957fea8e7cee ] + @@ -12 +13,0 @@ -Cc: stable@dpdk.org @@ -36 +37 @@ -index 285c6ddd61..0103add985 100644 +index 3f694a4d9a..bf8b3dbd36 100644 @@ -39 +40 @@ -@@ -415,7 +415,9 @@ gve_rx_queue_start_dqo(struct rte_eth_dev *dev, uint16_t rx_queue_id) +@@ -355,7 +355,9 @@ gve_rx_queue_start_dqo(struct rte_eth_dev *dev, uint16_t rx_queue_id) @@ -51 +52 @@ -index 169c40d5b0..c36c215b94 100644 +index 9550fe58c7..95a02bab17 100644 @@ -54 +55 @@ -@@ -531,7 +531,9 @@ gve_tx_queue_start_dqo(struct rte_eth_dev *dev, uint16_t tx_queue_id) +@@ -408,7 +408,9 @@ gve_tx_queue_start_dqo(struct rte_eth_dev *dev, uint16_t tx_queue_id)