From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7C97C470AE for ; Sun, 21 Dec 2025 16:01:19 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 73D7E4025F; Sun, 21 Dec 2025 16:01:19 +0100 (CET) Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011052.outbound.protection.outlook.com [40.93.194.52]) by mails.dpdk.org (Postfix) with ESMTP id C0E344025F for ; Sun, 21 Dec 2025 16:01:18 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=U0kHcBafsWru8l5EtCpmRAG34wnG5pDx+DXAOy7TYHoTsrTgKPRDw/XBpX/HmlyegIeN8jZKHWFyuhaG5jujs2v+LR9OwJS2VvXG3jpNOihYs4DJgkOBERWthefyRlS0PYGlk5VKAheXO0l6L9h7C7eSB2GbqrvweKBv6wBe++ZFpdA481fICUk546boC/vm/vpxklqATel+dHKCzqiqIp/DA/1VN2s55rJN43BCqx8V6JPKWQhqJA3uKNp6CChaqaMn1ZLWdNi9sOBMUFJ1J8MJiXa39tgXdEgXKljDe6VkWaUAzs6e33Vkb/qr/IiZlFKs86laPRHhW02OLvF9Sw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=vvtRuLySDgqbDWtKqOM1XPfCrJidG61z9tpqJAhx2Tk=; b=gla5v75P6LhYVZC+XcUaqYuBzWk42MZPDlKP04Zuua7MBpLkJloyM3Bmkqe0PyAow9sTExbd4eXRSmtGZhPAzRVppD7GH0WFeTFLDN1JitcwzO/inYwfRTlNQZos7YE3r+GRBfVRJ/hnVFb9ixKmhTYJmTDVefBsXtoGSPfVTvNFGwt38qbEQHA9tpbxs/8waW1OL9X+v9N8IdJ4E9755Q5r7TgghhJMV2X1McTXTrRotqUMGlUlKSz/LRTdEdVrhrLWvSR3Wv3XudZPMLpJSZ03nueinehLDC13GB5d+oBb0flTjUt1C+4gO33YYKyc9/k94JwlyASx4WVzUYckaA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=vvtRuLySDgqbDWtKqOM1XPfCrJidG61z9tpqJAhx2Tk=; b=INHRKj6k46Sf0qyiJFDtnVMKk020hk/+9gh3TwWBsaaaTRo0IQWUD/eitHaulwzboSQvgXDrWIxW4lqDU4wLjKrmxc2Ai70yIYZJVq0UGEMkxt4G8RRDzE5l+1EwTGdL84Ny0WfPDOj1UCvJnu3qgws2YpSwlrOrBf6I5OWl70SwFLK64oq19e6xh3JJ+ywxvrelsQChFtvRRVOCPCheSfhFwHM6zvFzyx9YX8mRmOlKgKvnE2lhxlSnVb4lfKHlJk4UrN7ckXZHW0fRYEobzK9xX320Eamc2a2kRCgXt1/4ls+QcivzUA2ngI+3vubJ8DG8RQxKmpknMBUj6L1Itg== Received: from MN2PR17CA0035.namprd17.prod.outlook.com (2603:10b6:208:15e::48) by SJ5PPFD525C5379.namprd12.prod.outlook.com (2603:10b6:a0f:fc02::9a3) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9434.10; Sun, 21 Dec 2025 15:01:12 +0000 Received: from BL6PEPF00022572.namprd02.prod.outlook.com (2603:10b6:208:15e:cafe::54) by MN2PR17CA0035.outlook.office365.com (2603:10b6:208:15e::48) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9434.9 via Frontend Transport; Sun, 21 Dec 2025 15:01:12 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL6PEPF00022572.mail.protection.outlook.com (10.167.249.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9456.9 via Frontend Transport; Sun, 21 Dec 2025 15:01:11 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sun, 21 Dec 2025 07:00:55 -0800 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sun, 21 Dec 2025 07:00:55 -0800 Received: from nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Sun, 21 Dec 2025 07:00:54 -0800 From: Shani Peretz To: Ciara Loftus CC: Bruce Richardson , dpdk stable Subject: patch 'net/iavf: fix Tx vector path selection logic' has been queued to stable release 23.11.6 Date: Sun, 21 Dec 2025 16:56:19 +0200 Message-ID: <20251221145746.763179-31-shperetz@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251221145746.763179-1-shperetz@nvidia.com> References: <20251221145746.763179-1-shperetz@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00022572:EE_|SJ5PPFD525C5379:EE_ X-MS-Office365-Filtering-Correlation-Id: a2de7524-1876-4cb6-6e86-08de40a1c7c4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|376014|82310400026|1800799024|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?ldh40/zmeqC3NYs0WenY16m5V+UhGAMARdnEHb10gHu1/+AomFLHg3cjaQ+B?= =?us-ascii?Q?fHNsGMg5EXPGMmhpdXfyrh9Kjv4gtz6CBTnPNfkp1p73j6EvzbPCGGpO2byP?= =?us-ascii?Q?yuy8nzwPJbq5qgfBVjlWiO4HQcVSfHFIqj6PRL8o2lnQNaEGG7/V53uPvyZc?= =?us-ascii?Q?MFarA78aXIEk+AlIzwItXV+VDU3F+1d8SZ5UYjMaM0CIautJyCKRLSWYmgAL?= =?us-ascii?Q?PEgbyaUJTS/I6vOu3FLbOeC20vuErp2TNHzXaUHH6gT58qeMMKBwgGNXtwoX?= =?us-ascii?Q?3JmKs60N1lm/tk/SBiN7L9EhOmIVXGJeNr1V8gpWHn1llCRLbD8ElIo1PgUm?= =?us-ascii?Q?sbvi0IP4sNf1W9odVtRc1pGwjGp+GVaS1NCgyMfmmhWaQPPXrjljtbEVBpTa?= =?us-ascii?Q?mgtLBXSQHZBUvpKC/LMDIvZMopB4V/nvuaMM+81/zavqXhsg2AZ4N56OPMK2?= =?us-ascii?Q?yACqzoLUyk/yGzZf3x6u/hPOemoacRQN0aAyntMJtsOWvnY7X1yfeK7COMoB?= =?us-ascii?Q?mvfKwLKlloO9AbmczynFrlw45a+iaTjjlJDYj09m/zev2x1MhTuEKYhG8wYd?= =?us-ascii?Q?lZXq0BhLcZPKFFvUztwVjiFlyyrka0bWS/rSDN4NCWZJfL+kmNOsZJ3574Q4?= =?us-ascii?Q?WoRE8rLbrj9C8enIRk6bXa7UYQidMBrIGJlR42aMdo1u0257p9Rp35lRlrax?= =?us-ascii?Q?a1qwqXraQab1/s0Kfsvor422KapEP0SVlTumUODtGlXuuf36bE057uxgOlj8?= =?us-ascii?Q?ZNBOxqncCG38NLlsXmjBBRjmPuNk05L93mF0w1FbosfRRmJd0C7WuzI2Kobt?= =?us-ascii?Q?Cf9uDc1tY3N0/WI9hsaGug0q3r4WjemJ9K0Pzp+ncqzmzvgkHwE4/mtypnXF?= =?us-ascii?Q?sdAMHQq7qQ9Yny9ky9U5TVbPziwLa/F1Zi1229pBMko/t2hIT7yr0uWj1xdu?= =?us-ascii?Q?n3PJVe2rttN+sRLLzcdjzUfGZHtHAnF0QSb7QNZAK2xCnuX0RQ0XHttZvR+c?= =?us-ascii?Q?7VdoYTEF57TA9zg3weC94XF+XOcJWb45wo4QjdbOZnIhwSB1biS9TbPenXzs?= =?us-ascii?Q?xuJoP5sqIsF1KrrfnSYmQ09Wbd73Aec7SysLAqjGrPaS9rSzLANCOimbnISK?= =?us-ascii?Q?dhkHlT7P/uAQi3Wgz4jHWahsyuQsUBiJ+dj0BpdquJqOR5J5qGrDykJVlqyV?= =?us-ascii?Q?fV3mgmOQsCUpIwtn0Lxe+oEuzs8WN93loWRz8UJf2QgMk4hdAjpjhnUaL53m?= =?us-ascii?Q?Brq/kPfRSeO/z/nENdKgUfT6Kq6TSzndPK1QAbAN/Hz80QB42W/4RD1rULuY?= =?us-ascii?Q?SK7OlChIqfv8O4mr+2NFfBvWdNSGm0B5aDJ8j5bTk/qCUhlcYL+Crk150lqI?= =?us-ascii?Q?h7R8tv+LJg0EzcIwxMBA710pv3jX+XIgbLeSdD9FbuT10nhMmmWa6c0IUyHe?= =?us-ascii?Q?dJ8I1GtgWrvylvezMBONJaRNEdfhr51phWrkD8osP2wFlo95MsQ5lk1BzXBU?= =?us-ascii?Q?JZQxq8POCKS7dYSOlkar812cG9KP9kchw2bkxhFXQYOXOoGzyc1lwXefix5B?= =?us-ascii?Q?U8VdIiTXwuSM5p5F+H3ho0Y2YD1KVhTgMA/GWDFf?= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024)(7053199007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Dec 2025 15:01:11.6781 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a2de7524-1876-4cb6-6e86-08de40a1c7c4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022572.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ5PPFD525C5379 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 23.11.6 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 12/26/25. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/shanipr/dpdk-stable This queued commit can be viewed at: https://github.com/shanipr/dpdk-stable/commit/9dca96d059a3bd5670a030298043a1db26afdd44 Thanks. Shani --- >From 9dca96d059a3bd5670a030298043a1db26afdd44 Mon Sep 17 00:00:00 2001 From: Ciara Loftus Date: Thu, 19 Jun 2025 13:36:57 +0000 Subject: [PATCH] net/iavf: fix Tx vector path selection logic [ upstream commit ecdccc79cf3296bb3cb6d53d87ad85d13828677b ] Prior to this change, it was possible the scalar path would be selected even if the AVX-512 path was available. This was due to the ordering of the logic in the iavf_set_tx_function function. Support for all three vector paths (sse, AVX2 and AVX-512) was first established and then in that order, the tx_burst_type was set to the appropriate type. If all three paths were supported, then the burst type would be first set to sse, then AVX2 then AVX-512. However, in the AVX2 logic, if an error was encountered then the burst type was set to a fallback option of the scalar path. This is not desired behaviour because the AVX-512 path should be selected over the scalar path when it is available. This commit fixes this issue by only checking for AVX2 support after deeming that AVX-512 is not supported. Fixes: 77b19d1d4b2e ("net/iavf: fix mbuf release path selection") Signed-off-by: Ciara Loftus Acked-by: Bruce Richardson --- drivers/net/iavf/iavf_rxtx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/iavf/iavf_rxtx.c b/drivers/net/iavf/iavf_rxtx.c index c4bd128043..9237f65936 100644 --- a/drivers/net/iavf/iavf_rxtx.c +++ b/drivers/net/iavf/iavf_rxtx.c @@ -3999,16 +3999,16 @@ iavf_set_tx_function(struct rte_eth_dev *dev) if (check_ret == IAVF_VECTOR_PATH) { use_sse = true; } - if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && - rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256) - use_avx2 = true; #ifdef CC_AVX512_SUPPORT if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 && rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 && rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512) use_avx512 = true; #endif + if (!use_avx512 && (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && + rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256) + use_avx2 = true; if (!use_sse && !use_avx2 && !use_avx512) goto normal; -- 2.43.0 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2025-12-21 16:54:18.933880596 +0200 +++ 0031-net-iavf-fix-Tx-vector-path-selection-logic.patch 2025-12-21 16:54:16.935032000 +0200 @@ -1 +1 @@ -From ecdccc79cf3296bb3cb6d53d87ad85d13828677b Mon Sep 17 00:00:00 2001 +From 9dca96d059a3bd5670a030298043a1db26afdd44 Mon Sep 17 00:00:00 2001 @@ -5,0 +6,2 @@ +[ upstream commit ecdccc79cf3296bb3cb6d53d87ad85d13828677b ] + @@ -21 +22,0 @@ -Cc: stable@dpdk.org @@ -26 +27 @@ - drivers/net/intel/iavf/iavf_rxtx.c | 8 ++++---- + drivers/net/iavf/iavf_rxtx.c | 8 ++++---- @@ -29,5 +30,5 @@ -diff --git a/drivers/net/intel/iavf/iavf_rxtx.c b/drivers/net/intel/iavf/iavf_rxtx.c -index 740876756b..5f5e3f047a 100644 ---- a/drivers/net/intel/iavf/iavf_rxtx.c -+++ b/drivers/net/intel/iavf/iavf_rxtx.c -@@ -4227,16 +4227,16 @@ iavf_set_tx_function(struct rte_eth_dev *dev) +diff --git a/drivers/net/iavf/iavf_rxtx.c b/drivers/net/iavf/iavf_rxtx.c +index c4bd128043..9237f65936 100644 +--- a/drivers/net/iavf/iavf_rxtx.c ++++ b/drivers/net/iavf/iavf_rxtx.c +@@ -3999,16 +3999,16 @@ iavf_set_tx_function(struct rte_eth_dev *dev)