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Sun, 21 Dec 2025 07:02:21 -0800 From: Shani Peretz To: Chengwen Feng CC: dpdk stable Subject: patch 'dma/hisilicon: fix stop with pending transfers' has been queued to stable release 23.11.6 Date: Sun, 21 Dec 2025 16:56:42 +0200 Message-ID: <20251221145746.763179-54-shperetz@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251221145746.763179-1-shperetz@nvidia.com> References: <20251221145746.763179-1-shperetz@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE2:EE_|LV3PR12MB9144:EE_ X-MS-Office365-Filtering-Correlation-Id: 9782d872-1568-4722-e564-08de40a1f4f6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|82310400026|376014|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?F8CacxggB0Q2iBLgETieeKTiUws3tia+Jtxb1TAan7+OhPhGiCyE35n723MW?= =?us-ascii?Q?jHTP27zWu2kVoXdVzjBpMuDgweFGy5dMLwNDnyZjSzOZ9sJEGNEgoZcuqpb1?= =?us-ascii?Q?9voJCQKTk3AubsI2u4rXDz95Sbf5+yiF3akByLRPwmizpUQJqG2TAcERNJIE?= =?us-ascii?Q?bJ+D8aJCbbdeE89/RgiEsMYAbIxpBw7X6qxccbEARcQTcyroQ3V/+VQh1X9+?= =?us-ascii?Q?cGDnQFU0LdaCPeocY7vNvm88apYKtBqfRdpLniQnfpYlVmKKtLgn6Wu3R9C9?= =?us-ascii?Q?KmBOyJP5Vab5+mn9gaDKQZXg/7ygEPLMLiHyXY9zMympGl1QgiuAV6SovmB5?= =?us-ascii?Q?c/Sf4ZvL9+srqilIOJ2zEyg/dR666T8htr7dYVSOwrZqCOnNvADvVTx8yqmv?= =?us-ascii?Q?+oJZ0z43EC7aNcuFlJyOFblXub9vVk1WfKdfp1rcSJYYIgGZuVEgBEsqnJJQ?= =?us-ascii?Q?2/IIuSiN2X/zxvY6yKQeLvPv9EJkQYEaOKhFRBle6m0HGa4wpRLzX+WiJUzq?= =?us-ascii?Q?9+t98kdqaUC2V0Jt0oncJ5taF10tWomr37PG0Z8rCBKt6VrSX9Wp8zenmuuT?= =?us-ascii?Q?QsgusYMt8oouCn+08WSaaSrpfkBIBvQUwfKWjirtdrKn4c0Fcg95RyiBjoq/?= =?us-ascii?Q?c+KkgT1Vbg8eO2LVlsjIaVvDJ7+LpFsGJnu+XEtKrSAl3b4RwbKTWLE6xcjB?= =?us-ascii?Q?39XfM8T293LDi/BTOAgVMlvF9Xveu1kWuLRrNq5NGSKgjj9JqVipkYPl+AjE?= =?us-ascii?Q?j2E24w4PwEbo71768PiOe9STDEbKrwXaGNcRV6Qd7kuxTH31G8k5/U2Yn8pw?= =?us-ascii?Q?asPbwgEss6UmS4nhq8q04OGVxCR56NxMfYHkynXOzB/RDbiKkGmk5L77nekl?= =?us-ascii?Q?mIYumQudV6i/fYmq9aT63JrK1ZoJVOZez7QMr1pYYQXxzoyLp22rnRKSLTlK?= =?us-ascii?Q?Y5XJ5vTj+W8j75htXN1o7RruW48XLv2tQURr+i3mJDY4m9SZHUhB1Tu/Sdxx?= =?us-ascii?Q?ZyGPgWSU8WQEB/wPuGMc6di7dywhkhSOXuDgClds02SECsjA7x8Jgt7bCzsU?= =?us-ascii?Q?hJDFmyQhtjQC69s4xskb8aE4nY10JD+O0lawoQRl5bODe24uH8Ln1EXYkvX0?= =?us-ascii?Q?RoICR3IUtXXRqllDSD6uxBUCjUKwBBFpLt+RN462tlU3DLpshThwmUf+t/0e?= =?us-ascii?Q?7q4c81J4i6OFvs9YhpU4ggV9PjeutLarGfah6CoDrqUL+ez0ZvbPc/fhUAAH?= =?us-ascii?Q?KaeCbSU77yRsGfSzjHkVzT24PtruADA/TeuRw7eEmeVDDe1x8psrO7S56WH7?= =?us-ascii?Q?prP8+ph1cEv1kr9XafK/uFDoWJQ0MgguXFh8Ooij/6kdIxHFeCMmzZeRohuk?= =?us-ascii?Q?SsZG0MvofDoMpCu8NCA2/7n2otpPx6M3g/+dmyoB6nWD1rn2lkYUCAN9s6fU?= =?us-ascii?Q?k9fb5lSxThFjo0J81i5Kb8q2quLt6yL9Hdy8gEc2Oxjy0nv+qJ/7sKlT6rFX?= =?us-ascii?Q?yr2jOlMLxh1d4jEJ6fcomzRk8bw7IRNaE90VGhlC6ggFiYXUsHZvcQckiGPv?= =?us-ascii?Q?HRUQrci15xr3iHi1njM=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014)(7053199007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Dec 2025 15:02:27.6753 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9782d872-1568-4722-e564-08de40a1f4f6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9144 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 23.11.6 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 12/26/25. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/shanipr/dpdk-stable This queued commit can be viewed at: https://github.com/shanipr/dpdk-stable/commit/36e492501873d8e692c050692c499e58b040b0b6 Thanks. Shani --- >From 36e492501873d8e692c050692c499e58b040b0b6 Mon Sep 17 00:00:00 2001 From: Chengwen Feng Date: Mon, 13 Oct 2025 17:22:11 +0800 Subject: [PATCH] dma/hisilicon: fix stop with pending transfers [ upstream commit 8aa458f1c44b9f6e73f75047aca77191dc79746f ] Stop dmadev may fail if there are pending DMA transfers, we need make sure there are no pending DMA transfers when stop. This commit uses following scheme: 1. flag stop proc so that new request will not process. 2. setting drop flag for all descriptor to quick complete. 3. waiting dmadev to complete. Fixes: 3c5f5f03a047 ("dma/hisilicon: add control path") Signed-off-by: Chengwen Feng --- drivers/dma/hisilicon/hisi_dmadev.c | 45 ++++++++++++++++++++++++----- drivers/dma/hisilicon/hisi_dmadev.h | 2 ++ 2 files changed, 39 insertions(+), 8 deletions(-) diff --git a/drivers/dma/hisilicon/hisi_dmadev.c b/drivers/dma/hisilicon/hisi_dmadev.c index 8bc076f5d5..cc171fa75c 100644 --- a/drivers/dma/hisilicon/hisi_dmadev.c +++ b/drivers/dma/hisilicon/hisi_dmadev.c @@ -378,6 +378,7 @@ hisi_dma_start(struct rte_dma_dev *dev) hw->cq_head = 0; hw->cqs_completed = 0; hw->cqe_vld = 1; + hw->stop_proc = 0; hw->submitted = 0; hw->completed = 0; hw->errors = 0; @@ -389,12 +390,6 @@ hisi_dma_start(struct rte_dma_dev *dev) return 0; } -static int -hisi_dma_stop(struct rte_dma_dev *dev) -{ - return hisi_dma_reset_hw(dev->data->dev_private); -} - static int hisi_dma_close(struct rte_dma_dev *dev) { @@ -456,6 +451,37 @@ hisi_dma_vchan_status(const struct rte_dma_dev *dev, uint16_t vchan, return 0; } +static int +hisi_dma_stop(struct rte_dma_dev *dev) +{ +#define MAX_WAIT_MSEC 10 + struct hisi_dma_dev *hw = dev->data->dev_private; + enum rte_dma_vchan_status status; + uint32_t i; + + /* Flag stop processing new requests. */ + hw->stop_proc = 1; + rte_delay_ms(1); + + /* Force set drop flag so that the hardware can quickly complete. */ + for (i = 0; i <= hw->sq_depth_mask; i++) + hw->sqe[i].dw0 |= SQE_DROP_FLAG; + + i = 0; + do { + hisi_dma_vchan_status(dev, 0, &status); + if (status != RTE_DMA_VCHAN_ACTIVE) + break; + rte_delay_ms(1); + } while (i++ < MAX_WAIT_MSEC); + if (status == RTE_DMA_VCHAN_ACTIVE) { + HISI_DMA_ERR(hw, "dev is still active!"); + return -EBUSY; + } + + return hisi_dma_reset_hw(dev->data->dev_private); +} + static void hisi_dma_dump_range(struct hisi_dma_dev *hw, FILE *f, uint32_t start, uint32_t end) @@ -550,14 +576,14 @@ hisi_dma_dump(const struct rte_dma_dev *dev, FILE *f) " revision: 0x%x queue_id: %u ring_size: %u\n" " ridx: %u cridx: %u\n" " sq_head: %u sq_tail: %u cq_sq_head: %u\n" - " cq_head: %u cqs_completed: %u cqe_vld: %u\n" + " cq_head: %u cqs_completed: %u cqe_vld: %u stop_proc: %u\n" " submitted: %" PRIu64 " completed: %" PRIu64 " errors: %" PRIu64 " qfulls: %" PRIu64 "\n", hw->revision, hw->queue_id, hw->sq_depth_mask > 0 ? hw->sq_depth_mask + 1 : 0, hw->ridx, hw->cridx, hw->sq_head, hw->sq_tail, hw->cq_sq_head, - hw->cq_head, hw->cqs_completed, hw->cqe_vld, + hw->cq_head, hw->cqs_completed, hw->cqe_vld, hw->stop_proc, hw->submitted, hw->completed, hw->errors, hw->qfulls); hisi_dma_dump_queue(hw, f); hisi_dma_dump_common(hw, f); @@ -575,6 +601,9 @@ hisi_dma_copy(void *dev_private, uint16_t vchan, RTE_SET_USED(vchan); + if (unlikely(hw->stop_proc > 0)) + return -EPERM; + if (((hw->sq_tail + 1) & hw->sq_depth_mask) == hw->sq_head) { hw->qfulls++; return -ENOSPC; diff --git a/drivers/dma/hisilicon/hisi_dmadev.h b/drivers/dma/hisilicon/hisi_dmadev.h index a57b5c759a..b9dd172c31 100644 --- a/drivers/dma/hisilicon/hisi_dmadev.h +++ b/drivers/dma/hisilicon/hisi_dmadev.h @@ -141,6 +141,7 @@ enum { struct hisi_dma_sqe { uint32_t dw0; +#define SQE_DROP_FLAG BIT(4) #define SQE_FENCE_FLAG BIT(10) #define SQE_OPCODE_M2M 0x4 uint32_t dw1; @@ -211,6 +212,7 @@ struct hisi_dma_dev { */ uint16_t cqs_completed; uint8_t cqe_vld; /**< valid bit for CQE, will change for every round. */ + volatile uint8_t stop_proc; /**< whether stop processing new requests. */ uint64_t submitted; uint64_t completed; -- 2.43.0 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2025-12-21 16:54:20.000907476 +0200 +++ 0054-dma-hisilicon-fix-stop-with-pending-transfers.patch 2025-12-21 16:54:17.129037000 +0200 @@ -1 +1 @@ -From 8aa458f1c44b9f6e73f75047aca77191dc79746f Mon Sep 17 00:00:00 2001 +From 36e492501873d8e692c050692c499e58b040b0b6 Mon Sep 17 00:00:00 2001 @@ -5,0 +6,2 @@ +[ upstream commit 8aa458f1c44b9f6e73f75047aca77191dc79746f ] + @@ -15 +16,0 @@ -Cc: stable@dpdk.org @@ -24 +25 @@ -index 019c4a8189..7575fb12d9 100644 +index 8bc076f5d5..cc171fa75c 100644 @@ -27 +28 @@ -@@ -376,6 +376,7 @@ hisi_dma_start(struct rte_dma_dev *dev) +@@ -378,6 +378,7 @@ hisi_dma_start(struct rte_dma_dev *dev) @@ -35 +36 @@ -@@ -387,12 +388,6 @@ hisi_dma_start(struct rte_dma_dev *dev) +@@ -389,12 +390,6 @@ hisi_dma_start(struct rte_dma_dev *dev) @@ -48 +49 @@ -@@ -454,6 +449,37 @@ hisi_dma_vchan_status(const struct rte_dma_dev *dev, uint16_t vchan, +@@ -456,6 +451,37 @@ hisi_dma_vchan_status(const struct rte_dma_dev *dev, uint16_t vchan, @@ -86 +87 @@ -@@ -548,14 +574,14 @@ hisi_dma_dump(const struct rte_dma_dev *dev, FILE *f) +@@ -550,14 +576,14 @@ hisi_dma_dump(const struct rte_dma_dev *dev, FILE *f) @@ -103 +104 @@ -@@ -573,6 +599,9 @@ hisi_dma_copy(void *dev_private, uint16_t vchan, +@@ -575,6 +601,9 @@ hisi_dma_copy(void *dev_private, uint16_t vchan, @@ -114 +115 @@ -index 90301e6b00..aab87c40be 100644 +index a57b5c759a..b9dd172c31 100644