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Sun, 21 Dec 2025 07:04:59 -0800 From: Shani Peretz To: Shai Brandes CC: Amit Bernstein , Yosef Raisman , dpdk stable Subject: patch 'net/ena: fix PCI BAR mapping on 64K page size' has been queued to stable release 23.11.6 Date: Sun, 21 Dec 2025 16:57:19 +0200 Message-ID: <20251221145746.763179-91-shperetz@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251221145746.763179-1-shperetz@nvidia.com> References: <20251221145746.763179-1-shperetz@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066ED:EE_|MN0PR12MB5857:EE_ X-MS-Office365-Filtering-Correlation-Id: 35798be0-18a3-4627-f26e-08de40a258e9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|376014|82310400026|1800799024|13003099007|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?79hLq2sdcqmwga5XZILtmwjmcd4+VSUlEG+iw1zlkhXw3vYRI5EtLZCId4YF?= =?us-ascii?Q?VfttjjS8nG0VgB4gi77gl3F9x6a9ZmwjHkAyEjoWC8Chy2rSgHyEi7uf2W5c?= =?us-ascii?Q?nHqpgOMrw2096z9ebMYtRlVP9LxZfz2yoiur6TXRJnkbwW/LkEb327YCpjz/?= =?us-ascii?Q?qaEeu2NotoJiRdbW7hQL81GZ0kJy/vMxGR80899r0G178Jsf2akxz9orB+Sb?= =?us-ascii?Q?EhvEmj7Wx4ndqnzPyECxKqUCSLZ9n60FG+G6z1wmgsXDZB/nd8kC+YXcw1iL?= =?us-ascii?Q?qMqTi3t3NAu42WLmnoelfeDrliyKvfFD4/UMsqZWMRHkmEAZnycDw1q/82FM?= =?us-ascii?Q?BFMv7LB402rNvv3QSVf2Ly8yONz/MoAawEROnFcdYKS5hn+aSt2QchMf+1X9?= =?us-ascii?Q?B1mr2UyFssiW7B+ywDvd9xgg4kyH+fVoeqGwoAvX/PldFm3bUexKYaAhJUrl?= =?us-ascii?Q?LAkyfxCk9Rp3WuNhPRetPc30eCw/hz6Mm4RYhTTPOJfxR75MngoDMDRx6wXV?= =?us-ascii?Q?HFhGpklTqrVUakN6KunGsj7VCN8Hxn0Zl3rh+bXOsgWauNyVXgUgCiU61n8W?= =?us-ascii?Q?wq4KKm9xpFhzYPzXFSVyxbVGyk4fG2ESdhsBRGZmF/j/En7T6eH3JNvHNE+b?= =?us-ascii?Q?9bAjMsZsWUr6l/FvXG2gHOWhsQGdezX+kYicPWCmIdK18Qt17alXW0uLYZcY?= =?us-ascii?Q?zbf9M+jhoB00SA0rWsn0j6LVNo9ZfKMmm4rTWDSDIY0aS9WE9u/GJhrZewW2?= =?us-ascii?Q?MbEbHWxdb8IQ7wYTappyQTuvRxHyeWy46tcePrCFxYcHo9+WXbwuCocCk3V4?= =?us-ascii?Q?0xPPlBhz7I8uUBVBkaoFpn9VYGLUFvTeB4dTdYCbn4Ef5BjQcUXmWt4nGToU?= =?us-ascii?Q?yf17K8m/kii3olF72K1ZWIeg0e5+xmVZYCICairCAeJe6Bjl2pA+q2WiAL7l?= =?us-ascii?Q?SAKP8aR5mBOkIFawE3EiB969efSSJiYrYndzw2SE/EWLNwtX2/3HsBp6I17D?= =?us-ascii?Q?TXc3BofZzjZl8lBhob7b5L+FnoyaLxxyVo1C1n4ylDkYrRPt+jjIlhftLhva?= =?us-ascii?Q?2HkrhyCG424ZXGANDR9eaoevU6Uqtv4lXLDs2JQHqG2EwCt8B/QzEis9Tkbz?= =?us-ascii?Q?MYd7yV2UlsyWQmiKEZni1LFC85JxMpyFphwlGOp08KONl9RnQjDVr7KkjVMM?= =?us-ascii?Q?77ovMk700cJ1qP5IYbMFgqlLfgKZXfCUKVwzwCUaMVAm4VMTRToCuGCiXpwZ?= =?us-ascii?Q?YJ53hINGU3UwwBQGwGgU5PE+wMNcIl4aSl+L4vo2UXn80CC65WlpgvhMpvkr?= =?us-ascii?Q?HWQ9d7COR2opRsvXHzonL2G7PjUAG6R23WZssmgqq8SKTtGqV/yaSUUFt46F?= =?us-ascii?Q?GgJIP18/E7jOhzdVTv9+qfQfj3xWzRsCY+qTC90N+i3PWS2ik00fXqVaqN3P?= =?us-ascii?Q?DnjG0GL4Zzg2JnfQw4SlJbi1ZF5lkIgKAznNj7kR5ta5nGImu+wsefFJJOMw?= =?us-ascii?Q?FxQsDYr2wvgLOUI3NEGvx+elsUICtScLtEzK8NIuBetRSYpY7TY8os8KeXG+?= =?us-ascii?Q?bFs9SlEAYP07yFgYdL0=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024)(13003099007)(7053199007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Dec 2025 15:05:15.2734 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 35798be0-18a3-4627-f26e-08de40a258e9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066ED.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5857 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 23.11.6 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 12/26/25. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/shanipr/dpdk-stable This queued commit can be viewed at: https://github.com/shanipr/dpdk-stable/commit/3b15d3623a511eee0c9dd55fbc9a6e2e13f8f7ef Thanks. Shani --- >From 3b15d3623a511eee0c9dd55fbc9a6e2e13f8f7ef Mon Sep 17 00:00:00 2001 From: Shai Brandes Date: Wed, 15 Oct 2025 15:09:16 +0300 Subject: [PATCH] net/ena: fix PCI BAR mapping on 64K page size [ upstream commit c71e3fbee65637084e1e42500e9e6300d50f467b ] On 64K page systems, DPDK `pci_uio` driver aligns the physical address to a 64K boundary before assigning a virtual address. If the original physical BAR address is not 64K-aligned, this adjustment leads to an incorrect mapping. This patch ensures the BAR virtual address received in the driver accounts for both PAGE size and BAR physical offset to correctly map each BAR. The fix is compatible for every PAGE size, applies to every used BAR, and supports both 32/64 bit DPDK builds. Example issue: - BAR0 physical address: 0x80208000 (not 64K-aligned) - DPDK aligned physical address: 0x80208000 -> 0x80200000 (masking 0x8000 offset) - DPDK mapped physical to virtual address: 0x80200000 -> 0x1140000000 - Driver accessed BAR0 virtual address = 0x1140000000 (causing init failure) - Resolution is to add correct offset to driver BAR0 address: 0x1140000000 + 0x8000 Fixes: 1173fca25af9 ("ena: add polling-mode driver") Signed-off-by: Amit Bernstein Signed-off-by: Shai Brandes Reviewed-by: Yosef Raisman --- drivers/net/ena/ena_ethdev.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index f3962aa76e..50cc4b76d1 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -8,6 +8,7 @@ #include #include #include +#include #include "ena_ethdev.h" #include "ena_logs.h" @@ -2165,6 +2166,24 @@ static int ena_init_once(void) return 0; } +/* + * Returns PCI BAR virtual address. + * If the physical address is not page-aligned, + * adjusts the virtual address by the page offset. + * Assumes page size is a power of 2. + */ +static void *pci_bar_addr(struct rte_pci_device *dev, uint32_t bar) +{ + const struct rte_mem_resource *res = &dev->mem_resource[bar]; + size_t offset = res->phys_addr % rte_mem_page_size(); + void *vaddr = RTE_PTR_ADD(res->addr, offset); + + PMD_INIT_LOG(INFO, "PCI BAR [%u]: phys_addr=0x%" PRIx64 ", addr=%p, offset=0x%zx, adjusted_addr=%p", + bar, res->phys_addr, res->addr, offset, vaddr); + + return vaddr; +} + static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) { struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 }; @@ -2209,16 +2228,17 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) intr_handle = pci_dev->intr_handle; - adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr; - adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr; - + adapter->regs = pci_bar_addr(pci_dev, ENA_REGS_BAR); if (!adapter->regs) { PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)\n", ENA_REGS_BAR); return -ENXIO; } - ena_dev->reg_bar = adapter->regs; + + /* Memory BAR may be NULL on non LLQ supported devices */ + adapter->dev_mem_base = pci_bar_addr(pci_dev, ENA_MEM_BAR); + /* Pass device data as a pointer which can be passed to the IO functions * by the ena_com (for example - the memory allocation). */ -- 2.43.0 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2025-12-21 16:54:21.642086941 +0200 +++ 0091-net-ena-fix-PCI-BAR-mapping-on-64K-page-size.patch 2025-12-21 16:54:17.432055000 +0200 @@ -1 +1 @@ -From c71e3fbee65637084e1e42500e9e6300d50f467b Mon Sep 17 00:00:00 2001 +From 3b15d3623a511eee0c9dd55fbc9a6e2e13f8f7ef Mon Sep 17 00:00:00 2001 @@ -5,0 +6,2 @@ +[ upstream commit c71e3fbee65637084e1e42500e9e6300d50f467b ] + @@ -27 +28,0 @@ -Cc: stable@dpdk.org @@ -33,16 +34,3 @@ - doc/guides/rel_notes/release_25_11.rst | 1 + - drivers/net/ena/ena_ethdev.c | 28 ++++++++++++++++++++++---- - 2 files changed, 25 insertions(+), 4 deletions(-) - -diff --git a/doc/guides/rel_notes/release_25_11.rst b/doc/guides/rel_notes/release_25_11.rst -index 94e5182016..863d111c8d 100644 ---- a/doc/guides/rel_notes/release_25_11.rst -+++ b/doc/guides/rel_notes/release_25_11.rst -@@ -109,6 +109,7 @@ New Features - * **Updated Amazon ENA (Elastic Network Adapter) ethernet driver.** - - * Added support for retrieving HW timestamps for Rx packets with nanosecond resolution. -+ * Fixed PCI BAR mapping on 64K page size. - - * **Added Huawei hinic3 ethernet driver.** - + drivers/net/ena/ena_ethdev.c | 28 ++++++++++++++++++++++++---- + 1 file changed, 24 insertions(+), 4 deletions(-) + @@ -50 +38 @@ -index 5147a754b2..aaa4feb11b 100644 +index f3962aa76e..50cc4b76d1 100644 @@ -53 +41 @@ -@@ -9,6 +9,7 @@ +@@ -8,6 +8,7 @@ @@ -61 +49 @@ -@@ -2364,6 +2365,24 @@ static int ena_init_once(void) +@@ -2165,6 +2166,24 @@ static int ena_init_once(void) @@ -77 +65 @@ -+ PMD_INIT_LOG_LINE(INFO, "PCI BAR [%u]: phys_addr=0x%" PRIx64 ", addr=%p, offset=0x%zx, adjusted_addr=%p", ++ PMD_INIT_LOG(INFO, "PCI BAR [%u]: phys_addr=0x%" PRIx64 ", addr=%p, offset=0x%zx, adjusted_addr=%p", @@ -86 +74 @@ -@@ -2409,16 +2428,17 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) +@@ -2209,16 +2228,17 @@ static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) @@ -95 +83 @@ - PMD_INIT_LOG_LINE(CRIT, "Failed to access registers BAR(%d)", + PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)\n",