* [PATCH] net/mlx5: fix the maximal queue size query
[not found] <CANDF9xANRqeTnkvAk61y=2TCd2fsWDQQ4YoTFdpL-RW8ksDDGQ@mail.gmail.com>
@ 2025-04-29 12:25 ` Viacheslav Ovsiienko
2025-05-14 7:55 ` [PATCH v2] " Viacheslav Ovsiienko
1 sibling, 0 replies; 3+ messages in thread
From: Viacheslav Ovsiienko @ 2025-04-29 12:25 UTC (permalink / raw)
To: dev; +Cc: rasland, matan, suanmingm, stable, Edwin Brossette, Dariusz Sosnowski
The mlx5 PMD manages the device using two modes: the Verbs API
and the DevX API. Each API offers its own method for querying
the maximum work queue size (in descriptors).
The corrected patch enhanced the rte_eth_dev_info_get() API
support in mlx5 PMD to return the true maximum number of descriptors.
It also implemented a limit check during queue creation, but this
was applied only to "DevX mode." Consequently, the "Verbs mode"
was overlooked, leading to malfunction on legacy NICs that do
not support DevX.
This patch adds support for Verbs mode, and all limit checks are
updated accordingly.
Fixes: 4c3d7961d900 ("net/mlx5: fix reported Rx/Tx descriptor limits")
Cc: stable@dpdk.org
Reported-by: Edwin Brossette <edwin.brossette@6wind.com>
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
drivers/common/mlx5/mlx5_prm.h | 1 +
drivers/net/mlx5/mlx5.h | 1 +
drivers/net/mlx5/mlx5_devx.c | 2 +-
drivers/net/mlx5/mlx5_ethdev.c | 39 +++++++++++++++++++++++++++++----
drivers/net/mlx5/mlx5_rxq.c | 2 +-
drivers/net/mlx5/mlx5_trigger.c | 4 ++--
drivers/net/mlx5/mlx5_txq.c | 12 +++++-----
7 files changed, 47 insertions(+), 14 deletions(-)
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 742c274a85..7accdeab87 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -41,6 +41,7 @@
/* Hardware index widths. */
#define MLX5_CQ_INDEX_WIDTH 24
#define MLX5_WQ_INDEX_WIDTH 16
+#define MLX5_WQ_INDEX_MAX (1u << (MLX5_WQ_INDEX_WIDTH - 1))
/* WQE Segment sizes in bytes. */
#define MLX5_WSEG_SIZE 16u
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 0194887a8b..ff182996d3 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -2303,6 +2303,7 @@ int mlx5_representor_info_get(struct rte_eth_dev *dev,
(((repr_id) >> 12) & 3)
uint16_t mlx5_representor_id_encode(const struct mlx5_switch_info *info,
enum rte_eth_representor_type hpf_type);
+uint16_t mlx5_dev_get_max_wq_size(struct mlx5_dev_ctx_shared *sh);
int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev,
diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c
index a12891a983..9711746edb 100644
--- a/drivers/net/mlx5/mlx5_devx.c
+++ b/drivers/net/mlx5/mlx5_devx.c
@@ -1593,7 +1593,7 @@ mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)
wqe_size = RTE_ALIGN(wqe_size, MLX5_WQE_SIZE) / MLX5_WQE_SIZE;
/* Create Send Queue object with DevX. */
wqe_n = RTE_MIN((1UL << txq_data->elts_n) * wqe_size,
- (uint32_t)priv->sh->dev_cap.max_qp_wr);
+ (uint32_t)mlx5_dev_get_max_wq_size(priv->sh));
log_desc_n = log2above(wqe_n);
ret = mlx5_txq_create_devx_sq_resources(dev, idx, log_desc_n);
if (ret) {
diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c
index 7708a0b808..7f12194f30 100644
--- a/drivers/net/mlx5/mlx5_ethdev.c
+++ b/drivers/net/mlx5/mlx5_ethdev.c
@@ -314,6 +314,37 @@ mlx5_set_txlimit_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
info->tx_desc_lim.nb_mtu_seg_max = nb_max;
}
+/**
+ * Get maximal work queue size in WQEs
+ *
+ * @param sh
+ * Pointer to the device shared context.
+ * @return
+ * Maximal number of WQEs in queue
+ */
+uint16_t
+mlx5_dev_get_max_wq_size(struct mlx5_dev_ctx_shared *sh)
+{
+ uint16_t max_wqe = MLX5_WQ_INDEX_MAX;
+
+ if (sh->cdev->config.devx) {
+ /* use HCA properties for DevX config */
+ MLX5_ASSERT(sh->cdev->config.hca_attr.log_max_wq_sz != 0);
+ MLX5_ASSERT(sh->cdev->config.hca_attr.log_max_wq_sz < MLX5_WQ_INDEX_WIDTH);
+ if (sh->cdev->config.hca_attr.log_max_wq_sz != 0 &&
+ sh->cdev->config.hca_attr.log_max_wq_sz < MLX5_WQ_INDEX_WIDTH)
+ max_wqe = 1u << sh->cdev->config.hca_attr.log_max_wq_sz;
+ } else {
+ /* use IB device capabilities */
+ MLX5_ASSERT(sh->dev_cap.max_qp_wr > 0);
+ MLX5_ASSERT(sh->dev_cap.max_qp_wr <= MLX5_WQ_INDEX_MAX);
+ if (sh->dev_cap.max_qp_wr > 0 &&
+ (uint32_t)sh->dev_cap.max_qp_wr <= MLX5_WQ_INDEX_MAX)
+ max_wqe = (uint16_t)sh->dev_cap.max_qp_wr;
+ }
+ return max_wqe;
+}
+
/**
* DPDK callback to get information about the device.
*
@@ -327,6 +358,7 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
{
struct mlx5_priv *priv = dev->data->dev_private;
unsigned int max;
+ uint16_t max_wqe;
/* FIXME: we should ask the device for these values. */
info->min_rx_bufsize = 32;
@@ -359,10 +391,9 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
info->flow_type_rss_offloads = ~MLX5_RSS_HF_MASK;
mlx5_set_default_params(dev, info);
mlx5_set_txlimit_params(dev, info);
- info->rx_desc_lim.nb_max =
- 1 << priv->sh->cdev->config.hca_attr.log_max_wq_sz;
- info->tx_desc_lim.nb_max =
- 1 << priv->sh->cdev->config.hca_attr.log_max_wq_sz;
+ max_wqe = mlx5_dev_get_max_wq_size(priv->sh);
+ info->rx_desc_lim.nb_max = max_wqe;
+ info->tx_desc_lim.nb_max = max_wqe;
if (priv->sh->cdev->config.hca_attr.mem_rq_rmp &&
priv->obj_ops.rxq_obj_new == devx_obj_ops.rxq_obj_new)
info->dev_capa |= RTE_ETH_DEV_CAPA_RXQ_SHARE;
diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c
index 5cf7d4971b..a8aaab13c8 100644
--- a/drivers/net/mlx5/mlx5_rxq.c
+++ b/drivers/net/mlx5/mlx5_rxq.c
@@ -655,7 +655,7 @@ mlx5_rx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc,
struct mlx5_rxq_priv *rxq;
bool empty;
- if (*desc > 1 << priv->sh->cdev->config.hca_attr.log_max_wq_sz) {
+ if (*desc > mlx5_dev_get_max_wq_size(priv->sh)) {
DRV_LOG(ERR,
"port %u number of descriptors requested for Rx queue"
" %u is more than supported",
diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c
index 4ee44e9165..8145ad4233 100644
--- a/drivers/net/mlx5/mlx5_trigger.c
+++ b/drivers/net/mlx5/mlx5_trigger.c
@@ -217,8 +217,8 @@ mlx5_rxq_start(struct rte_eth_dev *dev)
/* Should not release Rx queues but return immediately. */
return -rte_errno;
}
- DRV_LOG(DEBUG, "Port %u dev_cap.max_qp_wr is %d.",
- dev->data->port_id, priv->sh->dev_cap.max_qp_wr);
+ DRV_LOG(DEBUG, "Port %u max work queue size is %d.",
+ dev->data->port_id, mlx5_dev_get_max_wq_size(priv->sh));
DRV_LOG(DEBUG, "Port %u dev_cap.max_sge is %d.",
dev->data->port_id, priv->sh->dev_cap.max_sge);
for (i = 0; i != priv->rxqs_n; ++i) {
diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index 3e93517323..b14a1a4379 100644
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -333,7 +333,7 @@ mlx5_tx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc)
{
struct mlx5_priv *priv = dev->data->dev_private;
- if (*desc > 1 << priv->sh->cdev->config.hca_attr.log_max_wq_sz) {
+ if (*desc > mlx5_dev_get_max_wq_size(priv->sh)) {
DRV_LOG(ERR,
"port %u number of descriptors requested for Tx queue"
" %u is more than supported",
@@ -727,7 +727,7 @@ txq_calc_inline_max(struct mlx5_txq_ctrl *txq_ctrl)
struct mlx5_priv *priv = txq_ctrl->priv;
unsigned int wqe_size;
- wqe_size = priv->sh->dev_cap.max_qp_wr / desc;
+ wqe_size = mlx5_dev_get_max_wq_size(priv->sh) / desc;
if (!wqe_size)
return 0;
/*
@@ -1082,6 +1082,7 @@ mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
{
struct mlx5_priv *priv = dev->data->dev_private;
struct mlx5_txq_ctrl *tmpl;
+ uint16_t max_wqe;
tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl) +
desc * sizeof(struct rte_mbuf *), 0, socket);
@@ -1107,13 +1108,12 @@ mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
txq_set_params(tmpl);
if (txq_adjust_params(tmpl))
goto error;
- if (txq_calc_wqebb_cnt(tmpl) >
- priv->sh->dev_cap.max_qp_wr) {
+ max_wqe = mlx5_dev_get_max_wq_size(priv->sh);
+ if (txq_calc_wqebb_cnt(tmpl) > max_wqe) {
DRV_LOG(ERR,
"port %u Tx WQEBB count (%d) exceeds the limit (%d),"
" try smaller queue size",
- dev->data->port_id, txq_calc_wqebb_cnt(tmpl),
- priv->sh->dev_cap.max_qp_wr);
+ dev->data->port_id, txq_calc_wqebb_cnt(tmpl), max_wqe);
rte_errno = ENOMEM;
goto error;
}
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH v2] net/mlx5: fix the maximal queue size query
[not found] <CANDF9xANRqeTnkvAk61y=2TCd2fsWDQQ4YoTFdpL-RW8ksDDGQ@mail.gmail.com>
2025-04-29 12:25 ` [PATCH] net/mlx5: fix the maximal queue size query Viacheslav Ovsiienko
@ 2025-05-14 7:55 ` Viacheslav Ovsiienko
2025-05-14 9:22 ` Raslan Darawsheh
1 sibling, 1 reply; 3+ messages in thread
From: Viacheslav Ovsiienko @ 2025-05-14 7:55 UTC (permalink / raw)
To: dev; +Cc: rasland, matan, suanmingm, stable, Edwin Brossette, Dariusz Sosnowski
The mlx5 PMD manages the device using two modes: the Verbs API
and the DevX API. Each API offers its own method for querying
the maximum work queue size (in descriptors).
The corrected patch enhanced the rte_eth_dev_info_get() API
support in mlx5 PMD to return the true maximum number of descriptors.
It also implemented a limit check during queue creation, but this
was applied only to "DevX mode." Consequently, the "Verbs mode"
was overlooked, leading to malfunction on legacy NICs that do
not support DevX.
This patch adds support for Verbs mode, and all limit checks are
updated accordingly.
Fixes: 4c3d7961d900 ("net/mlx5: fix reported Rx/Tx descriptor limits")
Cc: stable@dpdk.org
Reported-by: Edwin Brossette <edwin.brossette@6wind.com>
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
v2 - minor fix for signed/unsigned comparison in debug assert
---
drivers/common/mlx5/mlx5_prm.h | 1 +
drivers/net/mlx5/mlx5.h | 1 +
drivers/net/mlx5/mlx5_devx.c | 2 +-
drivers/net/mlx5/mlx5_ethdev.c | 39 +++++++++++++++++++++++++++++----
drivers/net/mlx5/mlx5_rxq.c | 2 +-
drivers/net/mlx5/mlx5_trigger.c | 4 ++--
drivers/net/mlx5/mlx5_txq.c | 12 +++++-----
7 files changed, 47 insertions(+), 14 deletions(-)
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 86b09b6d0b..1e3ff26e43 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -41,6 +41,7 @@
/* Hardware index widths. */
#define MLX5_CQ_INDEX_WIDTH 24
#define MLX5_WQ_INDEX_WIDTH 16
+#define MLX5_WQ_INDEX_MAX (1u << (MLX5_WQ_INDEX_WIDTH - 1))
/* WQE Segment sizes in bytes. */
#define MLX5_WSEG_SIZE 16u
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 36f11b9c51..5695d0f54a 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -2303,6 +2303,7 @@ int mlx5_representor_info_get(struct rte_eth_dev *dev,
(((repr_id) >> 12) & 3)
uint16_t mlx5_representor_id_encode(const struct mlx5_switch_info *info,
enum rte_eth_representor_type hpf_type);
+uint16_t mlx5_dev_get_max_wq_size(struct mlx5_dev_ctx_shared *sh);
int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev,
diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c
index a12891a983..9711746edb 100644
--- a/drivers/net/mlx5/mlx5_devx.c
+++ b/drivers/net/mlx5/mlx5_devx.c
@@ -1593,7 +1593,7 @@ mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)
wqe_size = RTE_ALIGN(wqe_size, MLX5_WQE_SIZE) / MLX5_WQE_SIZE;
/* Create Send Queue object with DevX. */
wqe_n = RTE_MIN((1UL << txq_data->elts_n) * wqe_size,
- (uint32_t)priv->sh->dev_cap.max_qp_wr);
+ (uint32_t)mlx5_dev_get_max_wq_size(priv->sh));
log_desc_n = log2above(wqe_n);
ret = mlx5_txq_create_devx_sq_resources(dev, idx, log_desc_n);
if (ret) {
diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c
index 7708a0b808..a50320075c 100644
--- a/drivers/net/mlx5/mlx5_ethdev.c
+++ b/drivers/net/mlx5/mlx5_ethdev.c
@@ -314,6 +314,37 @@ mlx5_set_txlimit_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
info->tx_desc_lim.nb_mtu_seg_max = nb_max;
}
+/**
+ * Get maximal work queue size in WQEs
+ *
+ * @param sh
+ * Pointer to the device shared context.
+ * @return
+ * Maximal number of WQEs in queue
+ */
+uint16_t
+mlx5_dev_get_max_wq_size(struct mlx5_dev_ctx_shared *sh)
+{
+ uint16_t max_wqe = MLX5_WQ_INDEX_MAX;
+
+ if (sh->cdev->config.devx) {
+ /* use HCA properties for DevX config */
+ MLX5_ASSERT(sh->cdev->config.hca_attr.log_max_wq_sz != 0);
+ MLX5_ASSERT(sh->cdev->config.hca_attr.log_max_wq_sz < MLX5_WQ_INDEX_WIDTH);
+ if (sh->cdev->config.hca_attr.log_max_wq_sz != 0 &&
+ sh->cdev->config.hca_attr.log_max_wq_sz < MLX5_WQ_INDEX_WIDTH)
+ max_wqe = 1u << sh->cdev->config.hca_attr.log_max_wq_sz;
+ } else {
+ /* use IB device capabilities */
+ MLX5_ASSERT(sh->dev_cap.max_qp_wr > 0);
+ MLX5_ASSERT((unsigned int)sh->dev_cap.max_qp_wr <= MLX5_WQ_INDEX_MAX);
+ if (sh->dev_cap.max_qp_wr > 0 &&
+ (uint32_t)sh->dev_cap.max_qp_wr <= MLX5_WQ_INDEX_MAX)
+ max_wqe = (uint16_t)sh->dev_cap.max_qp_wr;
+ }
+ return max_wqe;
+}
+
/**
* DPDK callback to get information about the device.
*
@@ -327,6 +358,7 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
{
struct mlx5_priv *priv = dev->data->dev_private;
unsigned int max;
+ uint16_t max_wqe;
/* FIXME: we should ask the device for these values. */
info->min_rx_bufsize = 32;
@@ -359,10 +391,9 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
info->flow_type_rss_offloads = ~MLX5_RSS_HF_MASK;
mlx5_set_default_params(dev, info);
mlx5_set_txlimit_params(dev, info);
- info->rx_desc_lim.nb_max =
- 1 << priv->sh->cdev->config.hca_attr.log_max_wq_sz;
- info->tx_desc_lim.nb_max =
- 1 << priv->sh->cdev->config.hca_attr.log_max_wq_sz;
+ max_wqe = mlx5_dev_get_max_wq_size(priv->sh);
+ info->rx_desc_lim.nb_max = max_wqe;
+ info->tx_desc_lim.nb_max = max_wqe;
if (priv->sh->cdev->config.hca_attr.mem_rq_rmp &&
priv->obj_ops.rxq_obj_new == devx_obj_ops.rxq_obj_new)
info->dev_capa |= RTE_ETH_DEV_CAPA_RXQ_SHARE;
diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c
index ab29b43875..b676e5394b 100644
--- a/drivers/net/mlx5/mlx5_rxq.c
+++ b/drivers/net/mlx5/mlx5_rxq.c
@@ -656,7 +656,7 @@ mlx5_rx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc,
struct mlx5_rxq_priv *rxq;
bool empty;
- if (*desc > 1 << priv->sh->cdev->config.hca_attr.log_max_wq_sz) {
+ if (*desc > mlx5_dev_get_max_wq_size(priv->sh)) {
DRV_LOG(ERR,
"port %u number of descriptors requested for Rx queue"
" %u is more than supported",
diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c
index 4ee44e9165..8145ad4233 100644
--- a/drivers/net/mlx5/mlx5_trigger.c
+++ b/drivers/net/mlx5/mlx5_trigger.c
@@ -217,8 +217,8 @@ mlx5_rxq_start(struct rte_eth_dev *dev)
/* Should not release Rx queues but return immediately. */
return -rte_errno;
}
- DRV_LOG(DEBUG, "Port %u dev_cap.max_qp_wr is %d.",
- dev->data->port_id, priv->sh->dev_cap.max_qp_wr);
+ DRV_LOG(DEBUG, "Port %u max work queue size is %d.",
+ dev->data->port_id, mlx5_dev_get_max_wq_size(priv->sh));
DRV_LOG(DEBUG, "Port %u dev_cap.max_sge is %d.",
dev->data->port_id, priv->sh->dev_cap.max_sge);
for (i = 0; i != priv->rxqs_n; ++i) {
diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index ddd3a66282..5fee5bc4e8 100644
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -334,7 +334,7 @@ mlx5_tx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc)
{
struct mlx5_priv *priv = dev->data->dev_private;
- if (*desc > 1 << priv->sh->cdev->config.hca_attr.log_max_wq_sz) {
+ if (*desc > mlx5_dev_get_max_wq_size(priv->sh)) {
DRV_LOG(ERR,
"port %u number of descriptors requested for Tx queue"
" %u is more than supported",
@@ -728,7 +728,7 @@ txq_calc_inline_max(struct mlx5_txq_ctrl *txq_ctrl)
struct mlx5_priv *priv = txq_ctrl->priv;
unsigned int wqe_size;
- wqe_size = priv->sh->dev_cap.max_qp_wr / desc;
+ wqe_size = mlx5_dev_get_max_wq_size(priv->sh) / desc;
if (!wqe_size)
return 0;
/*
@@ -1054,6 +1054,7 @@ mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
{
struct mlx5_priv *priv = dev->data->dev_private;
struct mlx5_txq_ctrl *tmpl;
+ uint16_t max_wqe;
tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl) +
desc * sizeof(struct rte_mbuf *), 0, socket);
@@ -1078,13 +1079,12 @@ mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
tmpl->txq.idx = idx;
txq_set_params(tmpl);
txq_adjust_params(tmpl);
- if (txq_calc_wqebb_cnt(tmpl) >
- priv->sh->dev_cap.max_qp_wr) {
+ max_wqe = mlx5_dev_get_max_wq_size(priv->sh);
+ if (txq_calc_wqebb_cnt(tmpl) > max_wqe) {
DRV_LOG(ERR,
"port %u Tx WQEBB count (%d) exceeds the limit (%d),"
" try smaller queue size",
- dev->data->port_id, txq_calc_wqebb_cnt(tmpl),
- priv->sh->dev_cap.max_qp_wr);
+ dev->data->port_id, txq_calc_wqebb_cnt(tmpl), max_wqe);
rte_errno = ENOMEM;
goto error;
}
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] net/mlx5: fix the maximal queue size query
2025-05-14 7:55 ` [PATCH v2] " Viacheslav Ovsiienko
@ 2025-05-14 9:22 ` Raslan Darawsheh
0 siblings, 0 replies; 3+ messages in thread
From: Raslan Darawsheh @ 2025-05-14 9:22 UTC (permalink / raw)
To: Viacheslav Ovsiienko, dev
Cc: matan, suanmingm, stable, Edwin Brossette, Dariusz Sosnowski
Hi,
On 14/05/2025 10:55 AM, Viacheslav Ovsiienko wrote:
> The mlx5 PMD manages the device using two modes: the Verbs API
> and the DevX API. Each API offers its own method for querying
> the maximum work queue size (in descriptors).
>
> The corrected patch enhanced the rte_eth_dev_info_get() API
> support in mlx5 PMD to return the true maximum number of descriptors.
> It also implemented a limit check during queue creation, but this
> was applied only to "DevX mode." Consequently, the "Verbs mode"
> was overlooked, leading to malfunction on legacy NICs that do
> not support DevX.
>
> This patch adds support for Verbs mode, and all limit checks are
> updated accordingly.
>
> Fixes: 4c3d7961d900 ("net/mlx5: fix reported Rx/Tx descriptor limits")
> Cc: stable@dpdk.org
>
> Reported-by: Edwin Brossette <edwin.brossette@6wind.com>
> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
> Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
>
> ---
> v2 - minor fix for signed/unsigned comparison in debug assert
Patch applied to next-net-mlx,
--
Kindest regards
Raslan Darawsheh
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2025-05-14 9:23 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <CANDF9xANRqeTnkvAk61y=2TCd2fsWDQQ4YoTFdpL-RW8ksDDGQ@mail.gmail.com>
2025-04-29 12:25 ` [PATCH] net/mlx5: fix the maximal queue size query Viacheslav Ovsiienko
2025-05-14 7:55 ` [PATCH v2] " Viacheslav Ovsiienko
2025-05-14 9:22 ` Raslan Darawsheh
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).