Modify AFU configurations for new Blue Bitstream of A10 on N3000 card: - AFU register access: RTL changes the UPL base address and the read/write commands of register indirect access. - Add delays to wait for the HW reset completion. - Refine log for debug: print UPL_version not only for vBNG bit stream, but also for other bit streams Fixes: c01c748e4ae6 ("net/ipn3ke: add new driver") Cc: rosen.xu@intel.com Cc: stable@dpdk.org Signed-off-by: Dan Wei <dan.wei@intel.com> --- drivers/net/ipn3ke/ipn3ke_ethdev.c | 14 ++++++++++++-- drivers/net/ipn3ke/ipn3ke_ethdev.h | 9 +++++---- drivers/net/ipn3ke/ipn3ke_flow.c | 1 + 3 files changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.c b/drivers/net/ipn3ke/ipn3ke_ethdev.c index 9079b57..84eb0e9 100644 --- a/drivers/net/ipn3ke/ipn3ke_ethdev.c +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.c @@ -223,15 +223,25 @@ "LineSideMACType", &mac_type); hw->retimer.mac_type = (int)mac_type; + /* After power on, wait until init done */ + while (IPN3KE_READ_REG(hw, IPN3KE_INIT_DONE) != 0x3) + ; + + IPN3KE_AFU_PMD_DEBUG("UPL_version is 0x%x\n", IPN3KE_READ_REG(hw, 0)); + if (afu_dev->id.uuid.uuid_low == IPN3KE_UUID_VBNG_LOW && afu_dev->id.uuid.uuid_high == IPN3KE_UUID_VBNG_HIGH) { ipn3ke_hw_cap_init(hw); - IPN3KE_AFU_PMD_DEBUG("UPL_version is 0x%x\n", - IPN3KE_READ_REG(hw, 0)); /* Reset FPGA IP */ IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 1); + rte_delay_us(10); IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 0); + + /* After reset, wait until init done */ + while (IPN3KE_READ_REG(hw, IPN3KE_INIT_DONE) != 0x3) + ; + rte_delay_us(10); } if (hw->retimer.mac_type == IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI) { diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.h b/drivers/net/ipn3ke/ipn3ke_ethdev.h index bfda9d5..686c12f 100644 --- a/drivers/net/ipn3ke/ipn3ke_ethdev.h +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.h @@ -344,7 +344,6 @@ static inline uint32_t ipn3ke_read_addr(volatile void *addr) #define WCMD 0x8000000000000000 #define RCMD 0x4000000000000000 -#define UPL_BASE 0x10000 static inline uint32_t _ipn3ke_indrct_read(struct ipn3ke_hw *hw, uint32_t addr) { @@ -355,13 +354,13 @@ static inline uint32_t _ipn3ke_indrct_read(struct ipn3ke_hw *hw, word_offset = (addr & 0x1FFFFFF) >> 2; indirect_value = RCMD | word_offset << 32; - indirect_addrs = hw->hw_addr + (uint32_t)(UPL_BASE | 0x10); + indirect_addrs = hw->hw_addr + (uint32_t)(0x30); rte_delay_us(10); rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs); - indirect_addrs = hw->hw_addr + (uint32_t)(UPL_BASE | 0x18); + indirect_addrs = hw->hw_addr + (uint32_t)(0x38); while ((read_data >> 32) != 1) read_data = rte_read64(indirect_addrs); @@ -377,7 +376,7 @@ static inline void _ipn3ke_indrct_write(struct ipn3ke_hw *hw, word_offset = (addr & 0x1FFFFFF) >> 2; indirect_value = WCMD | word_offset << 32 | value; - indirect_addrs = hw->hw_addr + (uint32_t)(UPL_BASE | 0x10); + indirect_addrs = hw->hw_addr + (uint32_t)(0x30); rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs); rte_delay_us(10); @@ -411,6 +410,7 @@ static inline void _ipn3ke_indrct_write(struct ipn3ke_hw *hw, (&(((struct ipn3ke_rpst *)(dev)->data->dev_private)->tm)) /* Byte address of IPN3KE internal module */ +#define IPN3KE_INIT_DONE (0x204) #define IPN3KE_TM_VERSION (IPN3KE_QM_OFFSET + 0x0000) #define IPN3KE_TM_SCRATCH (IPN3KE_QM_OFFSET + 0x0004) #define IPN3KE_TM_STATUS (IPN3KE_QM_OFFSET + 0x0008) @@ -500,6 +500,7 @@ static inline void _ipn3ke_indrct_write(struct ipn3ke_hw *hw, #define IPN3KE_CLF_RX_TEST (IPN3KE_CLASSIFY_OFFSET + 0x0400) #define IPN3KE_CLF_EM_VERSION (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0000) +#define IPN3KE_CLF_EM_SCRATCH (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0004) #define IPN3KE_CLF_EM_NUM (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0008) #define IPN3KE_CLF_EM_KEY_WDTH (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x000C) #define IPN3KE_CLF_EM_RES_WDTH (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0010) diff --git a/drivers/net/ipn3ke/ipn3ke_flow.c b/drivers/net/ipn3ke/ipn3ke_flow.c index e5937df..ff9f064 100644 --- a/drivers/net/ipn3ke/ipn3ke_flow.c +++ b/drivers/net/ipn3ke/ipn3ke_flow.c @@ -1360,6 +1360,7 @@ int ipn3ke_flow_init(void *dev) IPN3KE_CLF_EM_NUM, 0, 0xFFFFFFFF); + IPN3KE_AFU_PMD_DEBUG("IPN3KE_CLF_EN_NUM: %x\n", hw->flow_max_entries); hw->flow_num_entries = 0; return 0; -- 1.8.3.1
Hi, > -----Original Message----- > From: Wei, Dan > Sent: Thursday, May 30, 2019 22:59 > To: dev@dpdk.org > Cc: Yigit, Ferruh <ferruh.yigit@intel.com>; Wei, Dan <dan.wei@intel.com>; > Xu, Rosen <rosen.xu@intel.com>; stable@dpdk.org > Subject: [DPDK v2] net/ipn3ke: modifications on AFU configurations > > Modify AFU configurations for new Blue Bitstream of A10 on N3000 card: Blue Bitstream is new term, pls explain it or take modification. > - AFU register access: RTL changes the UPL base address and the read/write > commands of register indirect access. What means UPL? Could you descript it in more common language? > - Add delays to wait for the HW reset completion. Does HW same means with RTL? > - Refine log for debug: print UPL_version not only for vBNG bit stream, but > also for other bit streams > > Fixes: c01c748e4ae6 ("net/ipn3ke: add new driver") > Cc: rosen.xu@intel.com > Cc: stable@dpdk.org > > Signed-off-by: Dan Wei <dan.wei@intel.com> > --- > drivers/net/ipn3ke/ipn3ke_ethdev.c | 14 ++++++++++++-- > drivers/net/ipn3ke/ipn3ke_ethdev.h | 9 +++++---- > drivers/net/ipn3ke/ipn3ke_flow.c | 1 + > 3 files changed, 18 insertions(+), 6 deletions(-) > > diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.c > b/drivers/net/ipn3ke/ipn3ke_ethdev.c > index 9079b57..84eb0e9 100644 > --- a/drivers/net/ipn3ke/ipn3ke_ethdev.c > +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.c > @@ -223,15 +223,25 @@ > "LineSideMACType", &mac_type); > hw->retimer.mac_type = (int)mac_type; > > + /* After power on, wait until init done */ > + while (IPN3KE_READ_REG(hw, IPN3KE_INIT_DONE) != 0x3) > + ; > + > + IPN3KE_AFU_PMD_DEBUG("UPL_version is 0x%x\n", > IPN3KE_READ_REG(hw, 0)); > + > if (afu_dev->id.uuid.uuid_low == IPN3KE_UUID_VBNG_LOW && > afu_dev->id.uuid.uuid_high == IPN3KE_UUID_VBNG_HIGH) { > ipn3ke_hw_cap_init(hw); > - IPN3KE_AFU_PMD_DEBUG("UPL_version is 0x%x\n", > - IPN3KE_READ_REG(hw, 0)); Why did you remove Debug code? > /* Reset FPGA IP */ > IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 1); > + rte_delay_us(10); > IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 0); > + > + /* After reset, wait until init done */ > + while (IPN3KE_READ_REG(hw, IPN3KE_INIT_DONE) != 0x3) > + ; > + rte_delay_us(10); > } > > if (hw->retimer.mac_type == > IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI) { diff --git > a/drivers/net/ipn3ke/ipn3ke_ethdev.h > b/drivers/net/ipn3ke/ipn3ke_ethdev.h > index bfda9d5..686c12f 100644 > --- a/drivers/net/ipn3ke/ipn3ke_ethdev.h > +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.h > @@ -344,7 +344,6 @@ static inline uint32_t ipn3ke_read_addr(volatile void > *addr) > > #define WCMD 0x8000000000000000 > #define RCMD 0x4000000000000000 > -#define UPL_BASE 0x10000 > static inline uint32_t _ipn3ke_indrct_read(struct ipn3ke_hw *hw, > uint32_t addr) > { > @@ -355,13 +354,13 @@ static inline uint32_t _ipn3ke_indrct_read(struct > ipn3ke_hw *hw, > > word_offset = (addr & 0x1FFFFFF) >> 2; > indirect_value = RCMD | word_offset << 32; > - indirect_addrs = hw->hw_addr + (uint32_t)(UPL_BASE | 0x10); > + indirect_addrs = hw->hw_addr + (uint32_t)(0x30); > > rte_delay_us(10); > > rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs); > > - indirect_addrs = hw->hw_addr + (uint32_t)(UPL_BASE | 0x18); > + indirect_addrs = hw->hw_addr + (uint32_t)(0x38); > while ((read_data >> 32) != 1) > read_data = rte_read64(indirect_addrs); > > @@ -377,7 +376,7 @@ static inline void _ipn3ke_indrct_write(struct > ipn3ke_hw *hw, > > word_offset = (addr & 0x1FFFFFF) >> 2; > indirect_value = WCMD | word_offset << 32 | value; > - indirect_addrs = hw->hw_addr + (uint32_t)(UPL_BASE | 0x10); > + indirect_addrs = hw->hw_addr + (uint32_t)(0x30); > > rte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs); > rte_delay_us(10); > @@ -411,6 +410,7 @@ static inline void _ipn3ke_indrct_write(struct > ipn3ke_hw *hw, > (&(((struct ipn3ke_rpst *)(dev)->data->dev_private)->tm)) > > /* Byte address of IPN3KE internal module */ > +#define IPN3KE_INIT_DONE (0x204) > #define IPN3KE_TM_VERSION (IPN3KE_QM_OFFSET + 0x0000) > #define IPN3KE_TM_SCRATCH (IPN3KE_QM_OFFSET + 0x0004) > #define IPN3KE_TM_STATUS (IPN3KE_QM_OFFSET + 0x0008) > @@ -500,6 +500,7 @@ static inline void _ipn3ke_indrct_write(struct > ipn3ke_hw *hw, > #define IPN3KE_CLF_RX_TEST (IPN3KE_CLASSIFY_OFFSET + 0x0400) > > #define IPN3KE_CLF_EM_VERSION (IPN3KE_CLASSIFY_OFFSET + 0x40000 > + 0x0000) > +#define IPN3KE_CLF_EM_SCRATCH (IPN3KE_CLASSIFY_OFFSET + 0x40000 > + 0x0004) > #define IPN3KE_CLF_EM_NUM (IPN3KE_CLASSIFY_OFFSET + 0x40000 + > 0x0008) > #define IPN3KE_CLF_EM_KEY_WDTH (IPN3KE_CLASSIFY_OFFSET + > 0x40000 + 0x000C) > #define IPN3KE_CLF_EM_RES_WDTH (IPN3KE_CLASSIFY_OFFSET + > 0x40000 + 0x0010) > diff --git a/drivers/net/ipn3ke/ipn3ke_flow.c > b/drivers/net/ipn3ke/ipn3ke_flow.c > index e5937df..ff9f064 100644 > --- a/drivers/net/ipn3ke/ipn3ke_flow.c > +++ b/drivers/net/ipn3ke/ipn3ke_flow.c > @@ -1360,6 +1360,7 @@ int ipn3ke_flow_init(void *dev) > IPN3KE_CLF_EM_NUM, > 0, > 0xFFFFFFFF); > + IPN3KE_AFU_PMD_DEBUG("IPN3KE_CLF_EN_NUM: %x\n", hw- > >flow_max_entries); > hw->flow_num_entries = 0; > > return 0; > -- > 1.8.3.1
Hi Rosen, thank you for your comments. > > > -----Original Message----- > > From: Wei, Dan > > Sent: Thursday, May 30, 2019 22:59 > > To: dev@dpdk.org > > Cc: Yigit, Ferruh <ferruh.yigit@intel.com>; Wei, Dan > > <dan.wei@intel.com>; Xu, Rosen <rosen.xu@intel.com>; stable@dpdk.org > > Subject: [DPDK v2] net/ipn3ke: modifications on AFU configurations > > > > Modify AFU configurations for new Blue Bitstream of A10 on N3000 card: > > Blue Bitstream is new term, pls explain it or take modification. BBS is the abbreviation of Blue Bitsteam. > > - AFU register access: RTL changes the UPL base address and the > > read/write commands of register indirect access. > > What means UPL? > Could you descript it in more common language? UPL is the abbreviation of User Programable Logic which is the cotainer of vBNG IP. > > - Add delays to wait for the HW reset completion. > > Does HW same means with RTL? It means RTL + DDR. > > - Refine log for debug: print UPL_version not only for vBNG bit > > stream, but also for other bit streams > > > > Fixes: c01c748e4ae6 ("net/ipn3ke: add new driver") > > Cc: rosen.xu@intel.com > > Cc: stable@dpdk.org > > > > Signed-off-by: Dan Wei <dan.wei@intel.com> > > --- > > drivers/net/ipn3ke/ipn3ke_ethdev.c | 14 ++++++++++++-- > > drivers/net/ipn3ke/ipn3ke_ethdev.h | 9 +++++---- > > drivers/net/ipn3ke/ipn3ke_flow.c | 1 + > > 3 files changed, 18 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.c > > b/drivers/net/ipn3ke/ipn3ke_ethdev.c > > index 9079b57..84eb0e9 100644 > > --- a/drivers/net/ipn3ke/ipn3ke_ethdev.c > > +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.c > > @@ -223,15 +223,25 @@ > > "LineSideMACType", &mac_type); > > hw->retimer.mac_type = (int)mac_type; > > > > + /* After power on, wait until init done */ > > + while (IPN3KE_READ_REG(hw, IPN3KE_INIT_DONE) != 0x3) > > + ; > > + > > + IPN3KE_AFU_PMD_DEBUG("UPL_version is 0x%x\n", > > IPN3KE_READ_REG(hw, 0)); > > + > > if (afu_dev->id.uuid.uuid_low == IPN3KE_UUID_VBNG_LOW && > > afu_dev->id.uuid.uuid_high == IPN3KE_UUID_VBNG_HIGH) { > > ipn3ke_hw_cap_init(hw); > > - IPN3KE_AFU_PMD_DEBUG("UPL_version is 0x%x\n", > > - IPN3KE_READ_REG(hw, 0)); > > Why did you remove Debug code? The debug code is moved up. Not only the version of vBNG Bitsteam, but also that of other bitsteams, should be printed out. > > /* Reset FPGA IP */ > > IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 1); > > + rte_delay_us(10); > > IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 0); > > + > > + /* After reset, wait until init done */ > > + while (IPN3KE_READ_REG(hw, IPN3KE_INIT_DONE) != 0x3) > > + ; > > + rte_delay_us(10); > > }
On 5/30/2019 3:58 PM, Dan Wei wrote: > Modify AFU configurations for new Blue Bitstream of A10 on N3000 card: > - AFU register access: RTL changes the UPL base address and the read/write > commands of register indirect access. > - Add delays to wait for the HW reset completion. > - Refine log for debug: print UPL_version not only for vBNG bit stream, > but also for other bit streams > > Fixes: c01c748e4ae6 ("net/ipn3ke: add new driver") > Cc: rosen.xu@intel.com > Cc: stable@dpdk.org > > Signed-off-by: Dan Wei <dan.wei@intel.com> > --- > drivers/net/ipn3ke/ipn3ke_ethdev.c | 14 ++++++++++++-- > drivers/net/ipn3ke/ipn3ke_ethdev.h | 9 +++++---- > drivers/net/ipn3ke/ipn3ke_flow.c | 1 + > 3 files changed, 18 insertions(+), 6 deletions(-) > > diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.c b/drivers/net/ipn3ke/ipn3ke_ethdev.c > index 9079b57..84eb0e9 100644 > --- a/drivers/net/ipn3ke/ipn3ke_ethdev.c > +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.c > @@ -223,15 +223,25 @@ > "LineSideMACType", &mac_type); > hw->retimer.mac_type = (int)mac_type; > > + /* After power on, wait until init done */ > + while (IPN3KE_READ_REG(hw, IPN3KE_INIT_DONE) != 0x3) > + ; Isn't this dangerous? What do you think putting a limit to the loop? And what do you think creating a define for 0x3? <...> > @@ -355,13 +354,13 @@ static inline uint32_t _ipn3ke_indrct_read(struct ipn3ke_hw *hw, > > word_offset = (addr & 0x1FFFFFF) >> 2; > indirect_value = RCMD | word_offset << 32; > - indirect_addrs = hw->hw_addr + (uint32_t)(UPL_BASE | 0x10); > + indirect_addrs = hw->hw_addr + (uint32_t)(0x30); Can you create a macro for 0x30 hardcoded value? And same for below hardcoded values. <...> > @@ -500,6 +500,7 @@ static inline void _ipn3ke_indrct_write(struct ipn3ke_hw *hw, > #define IPN3KE_CLF_RX_TEST (IPN3KE_CLASSIFY_OFFSET + 0x0400) > > #define IPN3KE_CLF_EM_VERSION (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0000) > +#define IPN3KE_CLF_EM_SCRATCH (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0004) As far as I can see this macro is not used in this patch, why adding it? <...>
Thank you for your comments. > > diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.c > > b/drivers/net/ipn3ke/ipn3ke_ethdev.c > > index 9079b57..84eb0e9 100644 > > --- a/drivers/net/ipn3ke/ipn3ke_ethdev.c > > +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.c > > @@ -223,15 +223,25 @@ > > "LineSideMACType", &mac_type); > > hw->retimer.mac_type = (int)mac_type; > > > > + /* After power on, wait until init done */ > > + while (IPN3KE_READ_REG(hw, IPN3KE_INIT_DONE) != 0x3) > > + ; > > Isn't this dangerous? What do you think putting a limit to the loop? > And what do you think creating a define for 0x3? I will add a timeout in the loop. I will create a macro for 0x3. > <...> > > > @@ -355,13 +354,13 @@ static inline uint32_t > > _ipn3ke_indrct_read(struct ipn3ke_hw *hw, > > > > word_offset = (addr & 0x1FFFFFF) >> 2; > > indirect_value = RCMD | word_offset << 32; > > - indirect_addrs = hw->hw_addr + (uint32_t)(UPL_BASE | 0x10); > > + indirect_addrs = hw->hw_addr + (uint32_t)(0x30); > > Can you create a macro for 0x30 hardcoded value? And same for below hardcoded values. I will create macros. > <...> > > > @@ -500,6 +500,7 @@ static inline void _ipn3ke_indrct_write(struct ipn3ke_hw *hw, > > #define IPN3KE_CLF_RX_TEST (IPN3KE_CLASSIFY_OFFSET + 0x0400) > > > > #define IPN3KE_CLF_EM_VERSION (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0000) > > +#define IPN3KE_CLF_EM_SCRATCH (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0004) > > As far as I can see this macro is not used in this patch, why adding it? I will delete it.
Hi Dan,
Thanks your clarify, pls apply them in new patch set, not just explain them in this patch.
> -----Original Message-----
> From: Wei, Dan
> Sent: Tuesday, June 04, 2019 11:19
> To: Xu, Rosen <rosen.xu@intel.com>; dev@dpdk.org
> Cc: Yigit, Ferruh <ferruh.yigit@intel.com>; stable@dpdk.org
> Subject: RE: [DPDK v2] net/ipn3ke: modifications on AFU configurations
>
> Hi Rosen, thank you for your comments.
>
> > > > -----Original Message-----
> > > From: Wei, Dan
> > > Sent: Thursday, May 30, 2019 22:59
> > > To: dev@dpdk.org
> > > Cc: Yigit, Ferruh <ferruh.yigit@intel.com>; Wei, Dan
> > > <dan.wei@intel.com>; Xu, Rosen <rosen.xu@intel.com>;
> stable@dpdk.org
> > > Subject: [DPDK v2] net/ipn3ke: modifications on AFU configurations
> > >
> > > Modify AFU configurations for new Blue Bitstream of A10 on N3000 card:
> >
> > Blue Bitstream is new term, pls explain it or take modification.
> BBS is the abbreviation of Blue Bitsteam.
>
> > > - AFU register access: RTL changes the UPL base address and the
> > > read/write commands of register indirect access.
> >
> > What means UPL?
> > Could you descript it in more common language?
> UPL is the abbreviation of User Programable Logic which is the cotainer of
> vBNG IP.
>
> > > - Add delays to wait for the HW reset completion.
> >
> > Does HW same means with RTL?
> It means RTL + DDR.
>
> > > - Refine log for debug: print UPL_version not only for vBNG bit
> > > stream, but also for other bit streams
> > >
> > > Fixes: c01c748e4ae6 ("net/ipn3ke: add new driver")
> > > Cc: rosen.xu@intel.com
> > > Cc: stable@dpdk.org
> > >
> > > Signed-off-by: Dan Wei <dan.wei@intel.com>
> > > ---
> > > drivers/net/ipn3ke/ipn3ke_ethdev.c | 14 ++++++++++++--
> > > drivers/net/ipn3ke/ipn3ke_ethdev.h | 9 +++++----
> > > drivers/net/ipn3ke/ipn3ke_flow.c | 1 +
> > > 3 files changed, 18 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.c
> > > b/drivers/net/ipn3ke/ipn3ke_ethdev.c
> > > index 9079b57..84eb0e9 100644
> > > --- a/drivers/net/ipn3ke/ipn3ke_ethdev.c
> > > +++ b/drivers/net/ipn3ke/ipn3ke_ethdev.c
> > > @@ -223,15 +223,25 @@
> > > "LineSideMACType", &mac_type);
> > > hw->retimer.mac_type = (int)mac_type;
> > >
> > > + /* After power on, wait until init done */
> > > + while (IPN3KE_READ_REG(hw, IPN3KE_INIT_DONE) != 0x3)
> > > + ;
> > > +
> > > + IPN3KE_AFU_PMD_DEBUG("UPL_version is 0x%x\n",
> > > IPN3KE_READ_REG(hw, 0));
> > > +
> > > if (afu_dev->id.uuid.uuid_low == IPN3KE_UUID_VBNG_LOW &&
> > > afu_dev->id.uuid.uuid_high == IPN3KE_UUID_VBNG_HIGH) {
> > > ipn3ke_hw_cap_init(hw);
> > > - IPN3KE_AFU_PMD_DEBUG("UPL_version is 0x%x\n",
> > > - IPN3KE_READ_REG(hw, 0));
> >
> > Why did you remove Debug code?
> The debug code is moved up. Not only the version of vBNG Bitsteam, but
> also
> that of other bitsteams, should be printed out.
> > > /* Reset FPGA IP */
> > > IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 1);
> > > + rte_delay_us(10);
> > > IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 0);
> > > +
> > > + /* After reset, wait until init done */
> > > + while (IPN3KE_READ_REG(hw, IPN3KE_INIT_DONE) != 0x3)
> > > + ;
> > > + rte_delay_us(10);
> > > }