From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 027D8A0A01 for ; Thu, 31 Dec 2020 07:07:16 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E790D140CCA; Thu, 31 Dec 2020 07:07:15 +0100 (CET) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 9F40D140CBC; Thu, 31 Dec 2020 07:07:13 +0100 (CET) IronPort-SDR: uQNUVOl0xjWmtob9x4HEVyUjipXignn8NtE0x8BK71eq9YmeCBaKnJ2w+gHU4WTB5yrZwqyYGA zh9B9pumM3iw== X-IronPort-AV: E=McAfee;i="6000,8403,9850"; a="240756677" X-IronPort-AV: E=Sophos;i="5.78,463,1599548400"; d="scan'208";a="240756677" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Dec 2020 22:07:12 -0800 IronPort-SDR: kvzeZMPnVMGtiq5NewLx4Nu0rIci51GoThTKXantjUhqGWYqk291weap8lTromajpTXq042rMw DFC8+2X4Kc2Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,463,1599548400"; d="scan'208";a="495148830" Received: from fmsmsx606.amr.corp.intel.com ([10.18.126.86]) by orsmga004.jf.intel.com with ESMTP; 30 Dec 2020 22:07:12 -0800 Received: from shsmsx605.ccr.corp.intel.com (10.109.6.215) by fmsmsx606.amr.corp.intel.com (10.18.126.86) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 30 Dec 2020 22:07:11 -0800 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by SHSMSX605.ccr.corp.intel.com (10.109.6.215) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 31 Dec 2020 14:07:09 +0800 Received: from shsmsx601.ccr.corp.intel.com ([10.109.6.141]) by SHSMSX601.ccr.corp.intel.com ([10.109.6.141]) with mapi id 15.01.1713.004; Thu, 31 Dec 2020 14:07:09 +0800 From: "Guo, Jia" To: "Xing, Beilei" , "dev@dpdk.org" CC: "stable@dpdk.org" , "Sun, Chenmin" Thread-Topic: [PATCH v3] net/i40e: fix flex payload rule conflict issue Thread-Index: AQHW3yr4/gQreIFh50ms0O1t3KRDs6oQs9JQ Date: Thu, 31 Dec 2020 06:07:09 +0000 Message-ID: <6828c56a8f01400c9cea311be2a6679d@intel.com> References: <20201229054639.92132-1-beilei.xing@intel.com> <20210101040341.21133-1-beilei.xing@intel.com> In-Reply-To: <20210101040341.21133-1-beilei.xing@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-stable] [PATCH v3] net/i40e: fix flex payload rule conflict issue X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" > -----Original Message----- > From: Xing, Beilei > Sent: Friday, January 1, 2021 12:04 PM > To: Guo, Jia ; dev@dpdk.org > Cc: Xing, Beilei ; stable@dpdk.org; Sun, Chenmin > > Subject: [PATCH v3] net/i40e: fix flex payload rule conflict issue >=20 > From: Beilei Xing >=20 > With the following commands, the second flow can't be created successfull= y. >=20 > 1. flow create 0 ingress pattern eth / ipv4 / udp / > raw relative is 1 pattern is 0102030405 / end > actions drop / end > 2. flow destroy 0 rule 0 > 3. flow create 0 ingress pattern eth / ipv4 / udp / > raw relative is 1 pattern is 010203040506 / end > actions drop / end >=20 > The root cause is that a flag for flex pit isn't reset. >=20 > Fixes: 6ced3dd72f5f ("net/i40e: support flexible payload parsing for FDIR= ") > Cc: stable@dpdk.org >=20 > Reported-by: Chenmin Sun > Signed-off-by: Beilei Xing > --- >=20 > v3 changes: > - Add flow count for flexible payload flow. > v2 changeds: > - Add fix line. >=20 > drivers/net/i40e/i40e_ethdev.h | 3 +++ > drivers/net/i40e/i40e_fdir.c | 16 ++++++++++++++-- > drivers/net/i40e/i40e_flow.c | 4 ++++ > 3 files changed, 21 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/net/i40e/i40e_ethdev.h > b/drivers/net/i40e/i40e_ethdev.h index 696c5aaf7e..aac226999c 100644 > --- a/drivers/net/i40e/i40e_ethdev.h > +++ b/drivers/net/i40e/i40e_ethdev.h > @@ -636,6 +636,7 @@ struct i40e_fdir_flow_ext { > bool is_udp; /* ipv4|ipv6 udp flow */ > enum i40e_flxpld_layer_idx layer_idx; > struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_LAYER * > I40E_MAX_FLXPLD_FIED]; > + bool is_flex_flow; > }; >=20 > /* A structure used to define the input for a flow director filter entry= */ @@ > -784,6 +785,8 @@ struct i40e_fdir_info { > bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX]; >=20 > bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set > */ > + > + uint32_t flex_flow_count[I40E_MAX_FLXPLD_LAYER]; > }; >=20 > /* Ethertype filter number HW supports */ diff --git > a/drivers/net/i40e/i40e_fdir.c b/drivers/net/i40e/i40e_fdir.c index > 50c0eee9f2..4400b607c8 100644 > --- a/drivers/net/i40e/i40e_fdir.c > +++ b/drivers/net/i40e/i40e_fdir.c > @@ -355,6 +355,7 @@ i40e_init_flx_pld(struct i40e_pf *pf) > I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non- > used*/ > I40E_WRITE_REG(hw, > I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non- > used*/ > + pf->fdir.flex_pit_flag[i] =3D 0; > } >=20 > /* initialize the masks */ > @@ -1513,8 +1514,6 @@ i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf, > I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), > flx_pit); > min_next_off++; > } > - > - pf->fdir.flex_pit_flag[layer_idx] =3D 1; > } >=20 > static int > @@ -1738,6 +1737,8 @@ i40e_flow_add_del_fdir_filter(struct rte_eth_dev > *dev, > fdir_info->fdir_guarantee_free_space > 0) > wait_status =3D false; > } else { > + layer_idx =3D filter->input.flow_ext.layer_idx; > + Assume that flow_ext.layer_idx should be assign to the layer_idx at the con= dition of " (!filter->input.flow_ext.customized_pctype) ", right? > node =3D i40e_sw_fdir_filter_lookup(fdir_info, > &check_filter.fdir.input); > if (!node) { > @@ -1785,6 +1786,17 @@ i40e_flow_add_del_fdir_filter(struct rte_eth_dev > *dev, > goto error_op; > } >=20 > + if (filter->input.flow_ext.is_flex_flow) { > + if (add) { > + fdir_info->flex_flow_count[layer_idx]++; > + pf->fdir.flex_pit_flag[layer_idx] =3D 1; > + } else { > + fdir_info->flex_flow_count[layer_idx]--; > + if (!fdir_info->flex_flow_count[layer_idx]) > + pf->fdir.flex_pit_flag[layer_idx] =3D 0; > + } > + } > + > if (add) { > fdir_info->fdir_actual_cnt++; > if (fdir_info->fdir_invalprio =3D=3D 1 && diff --git > a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c index > b09ff6590d..bbd666b7a0 100644 > --- a/drivers/net/i40e/i40e_flow.c > +++ b/drivers/net/i40e/i40e_flow.c > @@ -3069,6 +3069,7 @@ i40e_flow_parse_fdir_pattern(struct rte_eth_dev > *dev, > &flex_pit, sizeof(struct i40e_fdir_flex_pit)); > filter->input.flow_ext.layer_idx =3D layer_idx; > filter->input.flow_ext.raw_id =3D raw_id; > + filter->input.flow_ext.is_flex_flow =3D true; > break; > case RTE_FLOW_ITEM_TYPE_VF: > vf_spec =3D item->spec; > @@ -5515,6 +5516,9 @@ i40e_flow_flush_fdir_filter(struct i40e_pf *pf) > pf->fdir.flex_mask_flag[pctype] =3D 0; > } >=20 > + for (i =3D 0; i < I40E_MAX_FLXPLD_LAYER; i++) > + pf->fdir.flex_pit_flag[i] =3D 0; > + > /* Disable FDIR processing as all FDIR rules are now flushed > */ > i40e_fdir_rx_proc_enable(dev, 0); > } > -- > 2.26.2