* [dpdk-stable] [PATCH 20.11 1/3] event/octeontx2: fix crypto adapter queue pair operations
2021-06-16 18:42 [dpdk-stable] [PATCH 20.11 0/3] backport of octeontx2 patches Shijith Thotton
@ 2021-06-16 18:42 ` Shijith Thotton
2021-06-16 18:42 ` [dpdk-stable] [PATCH 20.11 2/3] event/octeontx2: configure crypto adapter xaq pool Shijith Thotton
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Shijith Thotton @ 2021-06-16 18:42 UTC (permalink / raw)
To: stable; +Cc: Shijith Thotton, xuemingl, pbhagavatula, Ankur Dwivedi
[ upstream commit 3841fc3581ec4d95bf8a72e8a545db8d03ecd2bd ]
Parameter queue_pair_id of crypto adapter queue pair add/del operation
can be -1 to select all pre configured crypto queue pairs. Added support
for the same in driver. Also added a member in cpt qp structure to
indicate binding state of a queue pair to an event queue.
Fixes: 29768f78d5a7 ("event/octeontx2: add crypto adapter framework")
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Acked-by: Ankur Dwivedi <adwivedi@marvell.com>
---
drivers/crypto/octeontx2/otx2_cryptodev_qp.h | 4 +-
.../event/octeontx2/otx2_evdev_crypto_adptr.c | 102 ++++++++++++------
2 files changed, 75 insertions(+), 31 deletions(-)
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_qp.h b/drivers/crypto/octeontx2/otx2_cryptodev_qp.h
index 96ff4eb41..499d54e3e 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_qp.h
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_qp.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
+ * Copyright (C) 2020-2021 Marvell.
*/
#ifndef _OTX2_CRYPTODEV_QP_H_
@@ -37,6 +37,8 @@ struct otx2_cpt_qp {
*/
uint8_t ca_enable;
/**< Set when queue pair is added to crypto adapter */
+ uint8_t qp_ev_bind;
+ /**< Set when queue pair is bound to event queue */
};
#endif /* _OTX2_CRYPTODEV_QP_H_ */
diff --git a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c
index 7197815ae..c6a4fbaf4 100644
--- a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c
+++ b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c
@@ -1,10 +1,11 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (C) 2020 Marvell International Ltd.
+ * Copyright (C) 2020-2021 Marvell.
*/
#include <rte_cryptodev.h>
#include <rte_eventdev.h>
+#include "otx2_cryptodev.h"
#include "otx2_cryptodev_hw_access.h"
#include "otx2_cryptodev_qp.h"
#include "otx2_cryptodev_mbox.h"
@@ -23,30 +24,66 @@ otx2_ca_caps_get(const struct rte_eventdev *dev,
return 0;
}
-int
-otx2_ca_qp_add(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev,
- int32_t queue_pair_id, const struct rte_event *event)
+static int
+otx2_ca_qp_sso_link(const struct rte_cryptodev *cdev, struct otx2_cpt_qp *qp,
+ uint16_t sso_pf_func)
{
- struct otx2_sso_evdev *sso_evdev = sso_pmd_priv(dev);
union otx2_cpt_af_lf_ctl2 af_lf_ctl2;
- struct otx2_cpt_qp *qp;
int ret;
- qp = cdev->data->queue_pairs[queue_pair_id];
-
- qp->ca_enable = 1;
- rte_memcpy(&qp->ev, event, sizeof(struct rte_event));
-
ret = otx2_cpt_af_reg_read(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),
- &af_lf_ctl2.u);
+ &af_lf_ctl2.u);
if (ret)
return ret;
- af_lf_ctl2.s.sso_pf_func = otx2_sso_pf_func_get();
+ af_lf_ctl2.s.sso_pf_func = sso_pf_func;
ret = otx2_cpt_af_reg_write(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),
- af_lf_ctl2.u);
- if (ret)
- return ret;
+ af_lf_ctl2.u);
+ return ret;
+}
+
+static void
+otx2_ca_qp_init(struct otx2_cpt_qp *qp, const struct rte_event *event)
+{
+ if (event) {
+ qp->qp_ev_bind = 1;
+ rte_memcpy(&qp->ev, event, sizeof(struct rte_event));
+ } else {
+ qp->qp_ev_bind = 0;
+ }
+ qp->ca_enable = 1;
+}
+
+int
+otx2_ca_qp_add(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev,
+ int32_t queue_pair_id, const struct rte_event *event)
+{
+ struct otx2_sso_evdev *sso_evdev = sso_pmd_priv(dev);
+ struct otx2_cpt_vf *vf = cdev->data->dev_private;
+ uint16_t sso_pf_func = otx2_sso_pf_func_get();
+ struct otx2_cpt_qp *qp;
+ uint8_t qp_id;
+ int ret;
+
+ if (queue_pair_id == -1) {
+ for (qp_id = 0; qp_id < vf->nb_queues; qp_id++) {
+ qp = cdev->data->queue_pairs[qp_id];
+ ret = otx2_ca_qp_sso_link(cdev, qp, sso_pf_func);
+ if (ret) {
+ uint8_t qp_tmp;
+ for (qp_tmp = 0; qp_tmp < qp_id; qp_tmp++)
+ otx2_ca_qp_del(dev, cdev, qp_tmp);
+ return ret;
+ }
+ otx2_ca_qp_init(qp, event);
+ }
+ } else {
+ qp = cdev->data->queue_pairs[queue_pair_id];
+ ret = otx2_ca_qp_sso_link(cdev, qp, sso_pf_func);
+ if (ret)
+ return ret;
+ otx2_ca_qp_init(qp, event);
+ }
sso_evdev->rx_offloads |= NIX_RX_OFFLOAD_SECURITY_F;
sso_fastpath_fns_set((struct rte_eventdev *)(uintptr_t)dev);
@@ -58,24 +95,29 @@ int
otx2_ca_qp_del(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev,
int32_t queue_pair_id)
{
- union otx2_cpt_af_lf_ctl2 af_lf_ctl2;
+ struct otx2_cpt_vf *vf = cdev->data->dev_private;
struct otx2_cpt_qp *qp;
+ uint8_t qp_id;
int ret;
RTE_SET_USED(dev);
- qp = cdev->data->queue_pairs[queue_pair_id];
- qp->ca_enable = 0;
- memset(&qp->ev, 0, sizeof(struct rte_event));
+ ret = 0;
+ if (queue_pair_id == -1) {
+ for (qp_id = 0; qp_id < vf->nb_queues; qp_id++) {
+ qp = cdev->data->queue_pairs[qp_id];
+ ret = otx2_ca_qp_sso_link(cdev, qp, 0);
+ if (ret)
+ return ret;
+ qp->ca_enable = 0;
+ }
+ } else {
+ qp = cdev->data->queue_pairs[queue_pair_id];
+ ret = otx2_ca_qp_sso_link(cdev, qp, 0);
+ if (ret)
+ return ret;
+ qp->ca_enable = 0;
+ }
- ret = otx2_cpt_af_reg_read(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),
- &af_lf_ctl2.u);
- if (ret)
- return ret;
-
- af_lf_ctl2.s.sso_pf_func = 0;
- ret = otx2_cpt_af_reg_write(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),
- af_lf_ctl2.u);
-
- return ret;
+ return 0;
}
--
2.25.1
^ permalink raw reply [flat|nested] 5+ messages in thread* [dpdk-stable] [PATCH 20.11 2/3] event/octeontx2: configure crypto adapter xaq pool
2021-06-16 18:42 [dpdk-stable] [PATCH 20.11 0/3] backport of octeontx2 patches Shijith Thotton
2021-06-16 18:42 ` [dpdk-stable] [PATCH 20.11 1/3] event/octeontx2: fix crypto adapter queue pair operations Shijith Thotton
@ 2021-06-16 18:42 ` Shijith Thotton
2021-06-16 18:42 ` [dpdk-stable] [PATCH 20.11 3/3] event/octeontx2: fix XAQ pool reconfigure Shijith Thotton
2021-06-17 2:54 ` [dpdk-stable] [PATCH 20.11 0/3] backport of octeontx2 patches Xueming(Steven) Li
3 siblings, 0 replies; 5+ messages in thread
From: Shijith Thotton @ 2021-06-16 18:42 UTC (permalink / raw)
To: stable; +Cc: Shijith Thotton, xuemingl, pbhagavatula
[ upstream commit 849111aec74dd3282a70b540683fcdc86be155d8 ]
Configure xaq pool based on number of in-use crypto queues to avoid CPT
add work failure due to xaq buffer run out. This patch configures
OTX2_CPT_DEFAULT_CMD_QLEN number of xae entries per queue pair.
Fixes: 29768f78d5a7 ("event/octeontx2: add crypto adapter framework")
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Acked-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
drivers/event/octeontx2/otx2_evdev_adptr.c | 2 +-
drivers/event/octeontx2/otx2_evdev_crypto_adptr.c | 8 ++++++++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/event/octeontx2/otx2_evdev_adptr.c b/drivers/event/octeontx2/otx2_evdev_adptr.c
index d69f269df..d85c3665c 100644
--- a/drivers/event/octeontx2/otx2_evdev_adptr.c
+++ b/drivers/event/octeontx2/otx2_evdev_adptr.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
+ * Copyright(C) 2019-2021 Marvell.
*/
#include "otx2_evdev.h"
diff --git a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c
index c6a4fbaf4..82bccd34e 100644
--- a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c
+++ b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c
@@ -88,6 +88,14 @@ otx2_ca_qp_add(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev,
sso_evdev->rx_offloads |= NIX_RX_OFFLOAD_SECURITY_F;
sso_fastpath_fns_set((struct rte_eventdev *)(uintptr_t)dev);
+ /* Update crypto adapter xae count */
+ if (queue_pair_id == -1)
+ sso_evdev->adptr_xae_cnt +=
+ vf->nb_queues * OTX2_CPT_DEFAULT_CMD_QLEN;
+ else
+ sso_evdev->adptr_xae_cnt += OTX2_CPT_DEFAULT_CMD_QLEN;
+ sso_xae_reconfigure((struct rte_eventdev *)(uintptr_t)dev);
+
return 0;
}
--
2.25.1
^ permalink raw reply [flat|nested] 5+ messages in thread* [dpdk-stable] [PATCH 20.11 3/3] event/octeontx2: fix XAQ pool reconfigure
2021-06-16 18:42 [dpdk-stable] [PATCH 20.11 0/3] backport of octeontx2 patches Shijith Thotton
2021-06-16 18:42 ` [dpdk-stable] [PATCH 20.11 1/3] event/octeontx2: fix crypto adapter queue pair operations Shijith Thotton
2021-06-16 18:42 ` [dpdk-stable] [PATCH 20.11 2/3] event/octeontx2: configure crypto adapter xaq pool Shijith Thotton
@ 2021-06-16 18:42 ` Shijith Thotton
2021-06-17 2:54 ` [dpdk-stable] [PATCH 20.11 0/3] backport of octeontx2 patches Xueming(Steven) Li
3 siblings, 0 replies; 5+ messages in thread
From: Shijith Thotton @ 2021-06-16 18:42 UTC (permalink / raw)
To: stable; +Cc: Pavan Nikhilesh, xuemingl
From: Pavan Nikhilesh <pbhagavatula@marvell.com>
[ upstream commit 052a5d38676373971cf2840c695a1421d2ac3045 ]
When XAQ pool is being re-configured, and if the same memzone
is used for fc_mem when freeing the old mempool the fc_mem
will be incorrectly updated with the free count.
Fixes: ffa4ec0b6063 ("event/octeontx2: allow adapters to resize inflight buffers")
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
drivers/common/octeontx2/otx2_mbox.h | 7 +++++++
drivers/event/octeontx2/otx2_evdev.c | 31 ++++++++++++++++++++++------
2 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/drivers/common/octeontx2/otx2_mbox.h b/drivers/common/octeontx2/otx2_mbox.h
index f6d884c19..51b25ab42 100644
--- a/drivers/common/octeontx2/otx2_mbox.h
+++ b/drivers/common/octeontx2/otx2_mbox.h
@@ -177,6 +177,8 @@ M(SSO_GRP_GET_STATS, 0x609, sso_grp_get_stats, sso_info_req, \
sso_grp_stats) \
M(SSO_HWS_GET_STATS, 0x610, sso_hws_get_stats, sso_info_req, \
sso_hws_stats) \
+M(SSO_HW_RELEASE_XAQ, 0x611, sso_hw_release_xaq_aura, \
+ sso_release_xaq, msg_rsp) \
/* TIM mbox IDs (range 0x800 - 0x9FF) */ \
M(TIM_LF_ALLOC, 0x800, tim_lf_alloc, tim_lf_alloc_req, \
tim_lf_alloc_rsp) \
@@ -1177,6 +1179,11 @@ struct sso_hw_setconfig {
uint16_t __otx2_io hwgrps;
};
+struct sso_release_xaq {
+ struct mbox_msghdr hdr;
+ uint16_t __otx2_io hwgrps;
+};
+
struct sso_info_req {
struct mbox_msghdr hdr;
union {
diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c
index 3afb5a30e..dd75b9f85 100644
--- a/drivers/event/octeontx2/otx2_evdev.c
+++ b/drivers/event/octeontx2/otx2_evdev.c
@@ -981,7 +981,7 @@ sso_xaq_allocate(struct otx2_sso_evdev *dev)
dev->fc_iova = mz->iova;
dev->fc_mem = mz->addr;
-
+ *dev->fc_mem = 0;
aura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem + OTX2_ALIGN);
memset(aura, 0, sizeof(struct npa_aura_s));
@@ -1057,6 +1057,19 @@ sso_ggrp_alloc_xaq(struct otx2_sso_evdev *dev)
return otx2_mbox_process(mbox);
}
+static int
+sso_ggrp_free_xaq(struct otx2_sso_evdev *dev)
+{
+ struct otx2_mbox *mbox = dev->mbox;
+ struct sso_release_xaq *req;
+
+ otx2_sso_dbg("Freeing XAQ for GGRPs");
+ req = otx2_mbox_alloc_msg_sso_hw_release_xaq_aura(mbox);
+ req->hwgrps = dev->nb_event_queues;
+
+ return otx2_mbox_process(mbox);
+}
+
static void
sso_lf_teardown(struct otx2_sso_evdev *dev,
enum otx2_sso_lf_type lf_type)
@@ -1447,6 +1460,8 @@ sso_cleanup(struct rte_eventdev *event_dev, uint8_t enable)
ssogws_reset((struct otx2_ssogws *)&ws->ws_state[1]);
ws->swtag_req = 0;
ws->vws = 0;
+ ws->fc_mem = dev->fc_mem;
+ ws->xaq_lmt = dev->xaq_lmt;
ws->ws_state[0].cur_grp = 0;
ws->ws_state[0].cur_tt = SSO_SYNC_EMPTY;
ws->ws_state[1].cur_grp = 0;
@@ -1457,6 +1472,8 @@ sso_cleanup(struct rte_eventdev *event_dev, uint8_t enable)
ws = event_dev->data->ports[i];
ssogws_reset(ws);
ws->swtag_req = 0;
+ ws->fc_mem = dev->fc_mem;
+ ws->xaq_lmt = dev->xaq_lmt;
ws->cur_grp = 0;
ws->cur_tt = SSO_SYNC_EMPTY;
}
@@ -1503,28 +1520,30 @@ int
sso_xae_reconfigure(struct rte_eventdev *event_dev)
{
struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
- struct rte_mempool *prev_xaq_pool;
int rc = 0;
if (event_dev->data->dev_started)
sso_cleanup(event_dev, 0);
- prev_xaq_pool = dev->xaq_pool;
+ rc = sso_ggrp_free_xaq(dev);
+ if (rc < 0) {
+ otx2_err("Failed to free XAQ\n");
+ return rc;
+ }
+
+ rte_mempool_free(dev->xaq_pool);
dev->xaq_pool = NULL;
rc = sso_xaq_allocate(dev);
if (rc < 0) {
otx2_err("Failed to alloc xaq pool %d", rc);
- rte_mempool_free(prev_xaq_pool);
return rc;
}
rc = sso_ggrp_alloc_xaq(dev);
if (rc < 0) {
otx2_err("Failed to alloc xaq to ggrp %d", rc);
- rte_mempool_free(prev_xaq_pool);
return rc;
}
- rte_mempool_free(prev_xaq_pool);
rte_mb();
if (event_dev->data->dev_started)
sso_cleanup(event_dev, 1);
--
2.25.1
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [dpdk-stable] [PATCH 20.11 0/3] backport of octeontx2 patches
2021-06-16 18:42 [dpdk-stable] [PATCH 20.11 0/3] backport of octeontx2 patches Shijith Thotton
` (2 preceding siblings ...)
2021-06-16 18:42 ` [dpdk-stable] [PATCH 20.11 3/3] event/octeontx2: fix XAQ pool reconfigure Shijith Thotton
@ 2021-06-17 2:54 ` Xueming(Steven) Li
3 siblings, 0 replies; 5+ messages in thread
From: Xueming(Steven) Li @ 2021-06-17 2:54 UTC (permalink / raw)
To: Shijith Thotton, stable; +Cc: pbhagavatula
Hi Shijith,
Thanks for providing the backport series, applied.
Xueming
> -----Original Message-----
> From: Shijith Thotton <sthotton@marvell.com>
> Sent: Thursday, June 17, 2021 2:42 AM
> To: stable@dpdk.org
> Cc: Shijith Thotton <sthotton@marvell.com>; Xueming(Steven) Li <xuemingl@nvidia.com>; pbhagavatula@marvell.com
> Subject: [PATCH 20.11 0/3] backport of octeontx2 patches
>
> Backported below octeontx2 patches for 20.11.
>
> Pavan Nikhilesh (1):
> event/octeontx2: fix XAQ pool reconfigure
>
> Shijith Thotton (2):
> event/octeontx2: fix crypto adapter queue pair operations
> event/octeontx2: configure crypto adapter xaq pool
>
> drivers/common/octeontx2/otx2_mbox.h | 7 ++
> drivers/crypto/octeontx2/otx2_cryptodev_qp.h | 4 +-
> drivers/event/octeontx2/otx2_evdev.c | 31 ++++-
> drivers/event/octeontx2/otx2_evdev_adptr.c | 2 +-
> .../event/octeontx2/otx2_evdev_crypto_adptr.c | 110 +++++++++++++-----
> 5 files changed, 116 insertions(+), 38 deletions(-)
>
> --
> 2.25.1
^ permalink raw reply [flat|nested] 5+ messages in thread