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From: Matan Azrad <matan@mellanox.com>
To: Slava Ovsiienko <viacheslavo@mellanox.com>,
	"dev@dpdk.org" <dev@dpdk.org>
Cc: Raslan Darawsheh <rasland@mellanox.com>,
	Ori Kam <orika@mellanox.com>, "stable@dpdk.org" <stable@dpdk.org>
Subject: Re: [dpdk-stable] [PATCH] net/mlx5: fix metadata item endianness conversion
Date: Mon, 6 Jan 2020 14:44:19 +0000
Message-ID: <AM0PR0502MB4019DEA4BEE490EB238EE66FD23C0@AM0PR0502MB4019.eurprd05.prod.outlook.com> (raw)
In-Reply-To: <1577197235-26433-1-git-send-email-viacheslavo@mellanox.com>



From: Viacheslav Ovsiienko
> The metadata register c0 field in the matcher might be split into two
> independent fields - the source vport index and META item value. These
> fields have no permanent assigned bits, the configuration is queried from the
> kernel drivers.
> 
> It means the metadata item field might be less than 32 bits.
> Also, the metadata are engaged in datapath and there are no any metadata
> endianness conversions in datapath to provide the better performance, all
> conversions are implemented in rte_flow engine. If there are less than 32
> bits of metadata the extra right shift is needed after endianness conversion
> for little- endian hosts.
> 
> Fixes: acfcd5c52f94 ("net/mlx5: update meta register matcher set")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>

  reply	other threads:[~2020-01-06 14:44 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-24 14:20 Viacheslav Ovsiienko
2020-01-06 14:44 ` Matan Azrad [this message]
2020-01-08  9:03 ` Raslan Darawsheh
2020-01-17 14:59 ` [dpdk-stable] [PATCH v2] " Viacheslav Ovsiienko
2020-01-17 17:19   ` Ferruh Yigit

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