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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN9PR11MB5483.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1fe500ad-87d5-49af-be84-08da54dc841c X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Jun 2022 05:52:11.1578 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: frv6iQ9ztLMBds1iDOhcxNHssXHIYzAH2q5Fxz/NC22eSBzZMp9jW5i4Ya5Ky4dJKqgPrtNYhg92B7hlLJqNEw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR11MB1547 X-OriginatorOrg: intel.com X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org > -----Original Message----- > From: Huang, Wei > Sent: Thursday, June 23, 2022 11:12 AM > To: dev@dpdk.org; thomas@monjalon.net; nipun.gupta@nxp.com; > hemant.agrawal@nxp.com > Cc: stable@dpdk.org; Xu, Rosen ; Zhang, Tianfei > ; Zhang, Qi Z ; Huang, Wei > > Subject: [PATCH] raw/ifpga: avoid potential integer overflow >=20 > Expression "tx_chunks * ctx->dma_buf_size" in dma_fpga_to_fpga() is evalu= ated > using 32-bit arithmetic, which would overflow potentially. Change tx_chu= nks to > type "uint64_t" to avoid such issue. >=20 > Coverity issue: 379203 > Fixes: 7d63899a5c19 ("raw/ifpga: add N3000 AFU driver") >=20 > Signed-off-by: Wei Huang > --- > drivers/raw/ifpga/afu_pmd_n3000.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/raw/ifpga/afu_pmd_n3000.c > b/drivers/raw/ifpga/afu_pmd_n3000.c > index 8708164..5120df5 100644 > --- a/drivers/raw/ifpga/afu_pmd_n3000.c > +++ b/drivers/raw/ifpga/afu_pmd_n3000.c > @@ -1158,7 +1158,7 @@ static int dma_fpga_to_fpga(struct dma_afu_ctx > *ctx, uint64_t dst, uint64_t src, > uint64_t count_left =3D count; > uint64_t dma_chunks =3D 0; > uint64_t offset =3D 0; > - uint32_t tx_chunks =3D 0; > + uint64_t tx_chunks =3D 0; > uint64_t *tmp_buf =3D NULL; > int ret =3D 0; >=20 > @@ -1213,7 +1213,7 @@ static int dma_fpga_to_fpga(struct dma_afu_ctx > *ctx, uint64_t dst, uint64_t src, > offset =3D tx_chunks * ctx->dma_buf_size; > count_left -=3D offset; > IFPGA_RAWDEV_PMD_DEBUG("0x%"PRIx64" --> 0x%"PRIx64 > - " (%u...0x%"PRIx64")", > + " (%"PRIu64"...0x%"PRIx64")", > src, dst, tx_chunks, count_left); > tmp_buf =3D (uint64_t *)rte_malloc(NULL, ctx->dma_buf_size, > DMA_ALIGN_BYTES); > -- > 1.8.3.1 It looks good for me. Acked-by: Tianfei Zhang