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From: Jerin Jacob Kollanukkaran <jerinj@marvell.com>
To: Bruce Richardson <bruce.richardson@intel.com>, hgovindh
<hariprasad.govindharajan@intel.com>
CC: Remy Horton <remy.horton@intel.com>, Marko Kovacevic
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Thread-Topic: [dpdk-dev] [PATCH v2] examples/l3fwd: fix unaligned memory access
Thread-Index: AQHVQwiDQov0aU8xcUyQGYouARGaGabbkVAA
Date: Thu, 25 Jul 2019 17:14:44 +0000
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<20190725164600.GA1621@bricha3-MOBL.ger.corp.intel.com>
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Subject: Re: [dpdk-stable] [dpdk-dev] [PATCH v2] examples/l3fwd: fix
unaligned memory access
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Sender: "stable" <stable-bounces@dpdk.org>
> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of Bruce Richardson
> Sent: Thursday, July 25, 2019 10:16 PM
> To: hgovindh <hariprasad.govindharajan@intel.com>
> Cc: Remy Horton <remy.horton@intel.com>; Marko Kovacevic
> <marko.kovacevic@intel.com>; Ori Kam <orika@mellanox.com>; Pablo de
> Lara <pablo.de.lara.guarch@intel.com>; Radu Nicolau
> <radu.nicolau@intel.com>; Akhil Goyal <akhil.goyal@nxp.com>; Tomasz
> Kantecki <tomasz.kantecki@intel.com>; dev@dpdk.org;
> maciej.czekaj@caviumnetworks.com; stable@dpdk.org
> Subject: Re: [dpdk-dev] [PATCH v2] examples/l3fwd: fix unaligned memory
> access
>=20
> On Thu, Jul 25, 2019 at 05:29:03PM +0100, hgovindh wrote:
> > Fix unaligned memory access when reading IPv6 header which leads to
> > segmentation fault by changing aligned memory read to unaligned memory
> > read.
> >
> > Bugzilla ID: 279
> > Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
> > Cc: maciej.czekaj@caviumnetworks.com
> > Cc: stable@dpdk.org
> > Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
> > ---
> > V2: Added functions which will do unaligned load based on the
> > underlying architecture
> > ---
> > ---
> > examples/l3fwd/l3fwd_em.c | 26 ++++++++++++++++++++++++--
> > 1 file changed, 24 insertions(+), 2 deletions(-)
> >
> > diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
> > index fa8f82be6..f2641586b 100644
> > --- a/examples/l3fwd/l3fwd_em.c
> > +++ b/examples/l3fwd/l3fwd_em.c
> > @@ -244,6 +244,29 @@ em_mask_key(void *key, xmm_t mask) #error No
> > vector engine (SSE, NEON, ALTIVEC) available, check your toolchain
> > #endif
> >
> > +#if defined(RTE_MACHINE_CPUFLAG_SSE2) static inline xmm_t
> > +em_load_key(void *key) {
> > + return _mm_loadu_si128((__m128i *)(key)); } #elif
> > +defined(RTE_MACHINE_CPUFLAG_NEON)
> > +static inline xmm_t
> > +em_load_key(void *key)
> > +{
> > + return vld1q_s32((int32_t *)key);
> > +}
> > +#elif defined(RTE_MACHINE_CPUFLAG_ALTIVEC)
> > +static inline xmm_t
> > +em_load_key(void *key)
> > +{
> > + return vec_ld(0, (xmm_t *)(key));
> > +}
Added power pc maintainer
Not sure all architecture need SIMD instructions for access to unaligned me=
mory location.
@hgovindh,
Could you provide exact setup details for reproducing this issue, I can tes=
t it on arm64.
Like l3fwd command, Traffic generator traffic pattern