From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 67F97A0C4C for ; Wed, 1 Dec 2021 11:31:52 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 52A2F40140; Wed, 1 Dec 2021 11:31:52 +0100 (CET) Received: from smtp-relay-internal-1.canonical.com (smtp-relay-internal-1.canonical.com [185.125.188.123]) by mails.dpdk.org (Postfix) with ESMTP id 5CF3940140 for ; Wed, 1 Dec 2021 11:31:51 +0100 (CET) Received: from mail-qv1-f71.google.com (mail-qv1-f71.google.com [209.85.219.71]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-1.canonical.com (Postfix) with ESMTPS id 332573F1B0 for ; Wed, 1 Dec 2021 10:31:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1638354711; bh=1E1o9CN/caUDjU+NJklDroXO6gwVfkFBwTihER4N2x4=; h=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject: To:Cc:Content-Type; b=IMDoMCfLXTWK8nPAA93LdGK/WDpQTof8o2e8yIIFPgp8pS0p0JX88cclHzNU5pXuY g1YFD+k2FtXADBkmo3L9fUoyDfm+G3Zzpd2U/oajewRNB13lucOwW/M0Oy6l+0E/Jo tAlg/g1gEqaYUqnG4ti+zbYrtJTkdoGVWc6MKcZIID1OgZ1hyhwOvqxq0BRGljgO6z kpd4OSwUA22xFmMK4CdPdfwJ6ksuKdN9hcFDOC3b/QRLezMQsZUhHIJGOB7wkhWZMG AVZlew0AkG3N6/Taogpzfzfgyx5GYJp2KgZ1X9z2m5kUfua/B8SXW43W2wSOXdOtC5 b+32jnCDVZNcA== Received: by mail-qv1-f71.google.com with SMTP id jn10-20020ad45dea000000b003bd74c93df4so33340612qvb.15 for ; Wed, 01 Dec 2021 02:31:51 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=1E1o9CN/caUDjU+NJklDroXO6gwVfkFBwTihER4N2x4=; b=dkbKw7bqSX678Qdh9ZT+lXFBQyQN0mv8+7f85SmERfhjCEd+ju1DnHvNxFkV7JwXsG QjlD2eBga1XspgNSK/lfzkCABXQ4dM7aTA0ym0AxV2Xn+oHUFBql0RBaiNsllavjpNsr K9YiA+wZ9TxSJs7lYpcCgQ7UIjFmyi3vE9n8xMgEv+1ee43XhFhxdog8CbFStMeb9Uez LkPD3h7eWQey3LDGj7NzuK3alz7i9SXFi8IPYC6H2fEM+Z2SW2b4VkRvu5s1fjPBUyXP 5GoGCxnRp834XuJg44CynIccQjG3XJ9JLG1ZK5H0xxsenDTHhTFFq0SZmupkDyA75Qob Fb9g== X-Gm-Message-State: AOAM530+kTmiztrJHtp002lgXNcwpsR39+JqRuwkG1PuE3yIPEGSwsZ3 X6S4rI1vDagPwD+epFY/r5YWB3UtqnVLyGIumzeDtt1uMK4KjOvVZ/IR1lQatjWRJIcjJpKyslB klCdt89B/X2Hp40lrG/0hw5l1xWPPMH5ouGBmqJFz X-Received: by 2002:a05:622a:100a:: with SMTP id d10mr5570329qte.548.1638354710021; Wed, 01 Dec 2021 02:31:50 -0800 (PST) X-Google-Smtp-Source: ABdhPJxbGp/BToX61DqHHWTt43uFw5OsP/Qfw/fWTS60ZTmA36THCsy7X8ITupZYl/ziLeiDIteZ2bamiioi6vDuiDY= X-Received: by 2002:a05:622a:100a:: with SMTP id d10mr5570306qte.548.1638354709825; Wed, 01 Dec 2021 02:31:49 -0800 (PST) MIME-Version: 1.0 References: <20211201074811.1590896-1-ruifeng.wang@arm.com> In-Reply-To: <20211201074811.1590896-1-ruifeng.wang@arm.com> From: Christian Ehrhardt Date: Wed, 1 Dec 2021 11:31:24 +0100 Message-ID: Subject: Re: [PATCH 19.11] net/i40e: fix risk in descriptor read in NEON Rx To: Ruifeng Wang Cc: stable@dpdk.org, nd@arm.com, Honnappa Nagarahalli Content-Type: text/plain; charset="UTF-8" X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org On Wed, Dec 1, 2021 at 8:48 AM Ruifeng Wang wrote: > > [ upstream commit 778602fe570a138224de94a38eca3ce2e344138c ] > Thanks, applied > Rx descriptor is 16B/32B in size. If the DD bit is set, it indicates > that the rest of the descriptor words have valid values. Hence, the > word containing DD bit must be read first before reading the rest of > the descriptor words. > > In NEON vector PMD, vector load loads two contiguous 8B of > descriptor data into vector register. Given vector load ensures no > 16B atomicity, read of the word that includes DD field could be > reordered after read of other words. In this case, some words could > contain invalid data. > > Read barrier is added after read of qword1 that includes DD field. > And qword0 is reloaded to update vector register. This ensures > that the fetched data is correct. > > Testpmd single core test on N1SDP/ThunderX2 showed no performance drop. > > Fixes: ae0eb310f253 ("net/i40e: implement vector PMD for ARM") > > Signed-off-by: Ruifeng Wang > Reviewed-by: Honnappa Nagarahalli > --- > drivers/net/i40e/i40e_rxtx_vec_neon.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/net/i40e/i40e_rxtx_vec_neon.c b/drivers/net/i40e/i40e_rxtx_vec_neon.c > index bd1e0490d..0da6b37da 100644 > --- a/drivers/net/i40e/i40e_rxtx_vec_neon.c > +++ b/drivers/net/i40e/i40e_rxtx_vec_neon.c > @@ -299,6 +299,14 @@ _recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts, > /* B.2 copy 2 mbuf point into rx_pkts */ > vst1q_u64((uint64_t *)&rx_pkts[pos + 2], mbp2); > > + /* Use acquire fence to order loads of descriptor qwords */ > + __atomic_thread_fence(__ATOMIC_ACQUIRE); > + /* A.2 reload qword0 to make it ordered after qword1 load */ > + descs[3] = vld1q_lane_u64((uint64_t *)(rxdp + 3), descs[3], 0); > + descs[2] = vld1q_lane_u64((uint64_t *)(rxdp + 2), descs[2], 0); > + descs[1] = vld1q_lane_u64((uint64_t *)(rxdp + 1), descs[1], 0); > + descs[0] = vld1q_lane_u64((uint64_t *)(rxdp), descs[0], 0); > + > if (split_packet) { > rte_mbuf_prefetch_part2(rx_pkts[pos]); > rte_mbuf_prefetch_part2(rx_pkts[pos + 1]); > -- > 2.25.1 > -- Christian Ehrhardt Staff Engineer, Ubuntu Server Canonical Ltd