From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id EA361A04DD for ; Thu, 19 Nov 2020 19:27:28 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id AE6AA2AB; Thu, 19 Nov 2020 19:27:27 +0100 (CET) Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by dpdk.org (Postfix) with ESMTP id 1B6222AB for ; Thu, 19 Nov 2020 19:27:26 +0100 (CET) Received: by mail-wr1-f67.google.com with SMTP id p8so7501093wrx.5 for ; Thu, 19 Nov 2020 10:27:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nfware-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=CtljBVzuR6OmKwbyceIqlRSXzEEAt3+o3JRtAsohJcg=; b=mNuRIykwR0iYDN9ap3Glpm2whEPHTLIycld3JyqcQwvaLVZZviZr9nMTqC/Ezm35dI ncp6zgOESt9ncIQ9Ompw13r3LIZxmA6TeMI+4kvt6SSVpkswHkecyPlIptUZFG/HZdP/ lxeWekuEC6KqaXW7XW5jlLFOaFZPsra3V4yGxOegXHuYgznOB9f/ztoBGphNWsYuXPCZ 0FDAAH8feahGdjrjCIc0IWdQFrYgY6xy1DGhHzq3QS6dT+1296hEU5QKccxqbGhu5Vgd vyqbbvLqDVDE9rEw7nhfIdTSTVJCIPGz98In7xCfq4lm6wMMBd9KNzJSNf0xTJ74WIeX goiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=CtljBVzuR6OmKwbyceIqlRSXzEEAt3+o3JRtAsohJcg=; b=UcRGTn3OS3UmlZ5HxJQ0wtMoWVcVicJsNY2YZEgzj4P2ERuPYgI7ClPtmmWuxSCZNf qKcbqxUJgahyGUx/h5QkBYr1Ul5oQWGL2m4LvUpJdW3AiJBPoeVJQwZ92PyjToAjwe+C ucdfw51DvkBSwqvbaD2Q4x+Xk9n2ggLW5o1XpBPbGOvmWD0ESJdH1cnCTg4wZmPzdDCE rSCoLIVfjwFZPDSrki4VLeopN7MIok0GzMHGjIljAFeQkIqByqfsdnTDCvXmz12MG0Vd 9namEHtZVjU9O2MdrsEEBZ5gCt9N8zDiG8+LZbRNkS4mbHX5X1EMDRCxGU0enEl07R2S neNw== X-Gm-Message-State: AOAM532cx2/Vdrjj7w4lqq7Mm+yBu5LLsjZWVJB1PH41mIBg5LiPxSu3 PKsDaYbkS9iTWGSQKNysNRr09dEl7V6N/IcC98X65g== X-Google-Smtp-Source: ABdhPJwi37AlMaQZZidroTTWIfhOiQ0hGJfGJmmxsGo+KNh0Wyn+lUTsoV4nmV17WUROLyYaNXJCJIyIfsKGqox0IJc= X-Received: by 2002:adf:a54d:: with SMTP id j13mr12427516wrb.132.1605810444702; Thu, 19 Nov 2020 10:27:24 -0800 (PST) MIME-Version: 1.0 References: <20201117085639.40307-1-iryzhov@nfware.com> In-Reply-To: <20201117085639.40307-1-iryzhov@nfware.com> From: Igor Ryzhov Date: Thu, 19 Nov 2020 21:27:13 +0300 Message-ID: To: dev Cc: dpdk stable , Beilei Xing , "Guo, Jia" , Thomas Monjalon Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Subject: Re: [dpdk-stable] [PATCH] net/i40e: fix counters X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" CC maintainers and Thomas. This fix should be 20.11. The issue is seen multiple times a day under ~20G traffic with stats collection once per second. Igor On Tue, Nov 17, 2020 at 11:56 AM Igor Ryzhov wrote: > When low and high registers are read separately, this opens the door to > a race condition: > - low register is read > - NIC updates the registers > - high register is read > > Because of this, we may end up with an incorrect counter value. > Let's read the registers in one shot, as it is done in Linux kernel > since the introduction of the i40e driver. > > Fixes: 4861cde46116 ("i40e: new poll mode driver") > Cc: stable@dpdk.org > Signed-off-by: Igor Ryzhov > --- > drivers/net/i40e/base/i40e_osdep.h | 10 ++++++++++ > drivers/net/i40e/i40e_ethdev.c | 10 +++++++--- > 2 files changed, 17 insertions(+), 3 deletions(-) > > diff --git a/drivers/net/i40e/base/i40e_osdep.h > b/drivers/net/i40e/base/i40e_osdep.h > index 64b15e1b6138..ebd687240006 100644 > --- a/drivers/net/i40e/base/i40e_osdep.h > +++ b/drivers/net/i40e/base/i40e_osdep.h > @@ -133,6 +133,14 @@ static inline uint32_t i40e_read_addr(volatile void > *addr) > return rte_le_to_cpu_32(I40E_PCI_REG(addr)); > } > > +#define I40E_PCI_REG64(reg) rte_read64(reg) > +#define I40E_PCI_REG64_ADDR(a, reg) \ > + ((volatile uint64_t *)((char *)(a)->hw_addr + (reg))) > +static inline uint64_t i40e_read64_addr(volatile void *addr) > +{ > + return rte_le_to_cpu_64(I40E_PCI_REG64(addr)); > +} > + > #define I40E_PCI_REG_WRITE(reg, value) \ > rte_write32((rte_cpu_to_le_32(value)), reg) > #define I40E_PCI_REG_WRITE_RELAXED(reg, value) \ > @@ -145,6 +153,8 @@ static inline uint32_t i40e_read_addr(volatile void > *addr) > #define I40E_WRITE_REG(hw, reg, value) \ > I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), (reg)), (value)) > > +#define I40E_READ_REG64(hw, reg) > i40e_read64_addr(I40E_PCI_REG64_ADDR((hw), (reg))) > + > #define rd32(a, reg) i40e_read_addr(I40E_PCI_REG_ADDR((a), (reg))) > #define wr32(a, reg, value) \ > I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((a), (reg)), (value)) > diff --git a/drivers/net/i40e/i40e_ethdev.c > b/drivers/net/i40e/i40e_ethdev.c > index 74f4ac1f9d4e..53b1e9b9e067 100644 > --- a/drivers/net/i40e/i40e_ethdev.c > +++ b/drivers/net/i40e/i40e_ethdev.c > @@ -6451,9 +6451,13 @@ i40e_stat_update_48(struct i40e_hw *hw, > { > uint64_t new_data; > > - new_data = (uint64_t)I40E_READ_REG(hw, loreg); > - new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) & > - I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH; > + if (hw->device_id == I40E_DEV_ID_QEMU) { > + new_data = (uint64_t)I40E_READ_REG(hw, loreg); > + new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) & > + I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH; > + } else { > + new_data = I40E_READ_REG64(hw, loreg); > + } > > if (!offset_loaded) > *offset = new_data; > -- > 2.29.2 > >