patches for DPDK stable branches
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From: "Xueming(Steven) Li" <xuemingl@nvidia.com>
To: Slava Ovsiienko <viacheslavo@nvidia.com>,
	"stable@dpdk.org" <stable@dpdk.org>
Cc: "bluca@debian.org" <bluca@debian.org>
Subject: Re: [dpdk-stable] [PATCH 20.11] net/mlx5: support timestamp format
Date: Mon, 31 May 2021 11:33:40 +0000
Message-ID: <DM4PR12MB53732F31144051B9C74B6072A13F9@DM4PR12MB5373.namprd12.prod.outlook.com> (raw)
In-Reply-To: <20210519185037.31224-1-viacheslavo@nvidia.com>

Thanks, applied to work queue.

> -----Original Message-----
> From: Slava Ovsiienko <viacheslavo@nvidia.com>
> Sent: Thursday, May 20, 2021 2:51 AM
> To: stable@dpdk.org
> Cc: bluca@debian.org; Xueming(Steven) Li <xuemingl@nvidia.com>
> Subject: [PATCH 20.11] net/mlx5: support timestamp format
> 
> [ upstream commit d61381ad46d0c42a4d8ab08742ae63d61ca0f53e ]
> 
> This patch adds support for the timestamp format settings for the receive and send queues. If the firmware version x.30.1000 or
> above is installed and the NIC timestamps are configured with the real-time format, the default zero values for newly added fields
> cause the queue creation to fail.
> 
> The patch queries the timestamp formats supported by the hardware and sets the configuration values in queue context accordingly.
> 
> Fixes: 86fc67fc9315 ("net/mlx5: create advanced RxQ object via DevX")
> Fixes: ae18a1ae9692 ("net/mlx5: support Tx hairpin queues")
> Fixes: 15c3807e86ab ("common/mlx5: support DevX QP operations")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
> Acked-by: Matan Azrad <matan@nvidia.com>
> Acked-by: Ori Kam <orika@nvidia.com>
> ---
>  drivers/net/mlx5/linux/mlx5_os.c | 3 +++
>  drivers/net/mlx5/mlx5.h          | 3 +++
>  drivers/net/mlx5/mlx5_devx.c     | 1 +
>  drivers/net/mlx5/mlx5_flow_age.c | 5 +++--
>  drivers/net/mlx5/mlx5_txpp.c     | 2 ++
>  5 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c
> index fb385460e5..b907e6de16 100644
> --- a/drivers/net/mlx5/linux/mlx5_os.c
> +++ b/drivers/net/mlx5/linux/mlx5_os.c
> @@ -1119,6 +1119,9 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
>  			sh->cmng.relaxed_ordering_read = 0;
>  			sh->cmng.relaxed_ordering_write = 0;
>  		}
> +		sh->rq_ts_format = config->hca_attr.rq_ts_format;
> +		sh->sq_ts_format = config->hca_attr.sq_ts_format;
> +		sh->qp_ts_format = config->hca_attr.qp_ts_format;
>  		/* Check for LRO support. */
>  		if (config->dest_tir && config->hca_attr.lro_cap &&
>  		    config->dv_flow_en) {
> diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 97f8a016b4..cd701880ee 100644
> --- a/drivers/net/mlx5/mlx5.h
> +++ b/drivers/net/mlx5/mlx5.h
> @@ -689,6 +689,9 @@ struct mlx5_dev_ctx_shared {
>  	uint16_t bond_dev; /* Bond primary device id. */
>  	uint32_t devx:1; /* Opened with DV. */
>  	uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */
> +	uint32_t rq_ts_format:2; /* RQ timestamp formats supported. */
> +	uint32_t sq_ts_format:2; /* SQ timestamp formats supported. */
> +	uint32_t qp_ts_format:2; /* QP timestamp formats supported. */
>  	uint32_t eqn; /* Event Queue number. */
>  	uint32_t max_port; /* Maximal IB device port index. */
>  	void *ctx; /* Verbs/DV/DevX context. */ diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index
> 9970a58156..377362e321 100644
> --- a/drivers/net/mlx5/mlx5_devx.c
> +++ b/drivers/net/mlx5/mlx5_devx.c
> @@ -1369,6 +1369,7 @@ mlx5_txq_create_devx_sq_resources(struct rte_eth_dev *dev, uint16_t idx,
>  	sq_attr.allow_multi_pkt_send_wqe = !!priv->config.mps;
>  	sq_attr.allow_swp = !!priv->config.swp;
>  	sq_attr.min_wqe_inline_mode = priv->config.hca_attr.vport_inline_mode;
> +	sq_attr.ts_format = mlx5_ts_format_conv(priv->sh->sq_ts_format);
>  	sq_attr.wq_attr.uar_page =
>  				mlx5_os_get_devx_uar_page_id(priv->sh->tx_uar);
>  	sq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC; diff --git a/drivers/net/mlx5/mlx5_flow_age.c
> b/drivers/net/mlx5/mlx5_flow_age.c
> index 0ea61be4eb..6c4ee0d33c 100644
> --- a/drivers/net/mlx5/mlx5_flow_age.c
> +++ b/drivers/net/mlx5/mlx5_flow_age.c
> @@ -257,7 +257,7 @@ mlx5_aso_init_sq(struct mlx5_aso_sq *sq)  static int  mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq,
> int socket,
>  		   struct mlx5dv_devx_uar *uar, uint32_t pdn,
> -		   uint32_t eqn,  uint16_t log_desc_n)
> +		   uint32_t eqn,  uint16_t log_desc_n, uint32_t ts_format)
>  {
>  	struct mlx5_devx_create_sq_attr attr = { 0 };
>  	struct mlx5_devx_modify_sq_attr modify_attr = { 0 }; @@ -296,6 +296,7 @@ mlx5_aso_sq_create(void *ctx, struct
> mlx5_aso_sq *sq, int socket,
>  	attr.tis_num = 0;
>  	attr.user_index = 0xFFFF;
>  	attr.cqn = sq->cq.cq->id;
> +	attr.ts_format = mlx5_ts_format_conv(ts_format);
>  	wq_attr->uar_page = mlx5_os_get_devx_uar_page_id(uar);
>  	wq_attr->pd = pdn;
>  	wq_attr->wq_type = MLX5_WQ_TYPE_CYCLIC; @@ -348,7 +349,7 @@ mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh)
> {
>  	return mlx5_aso_sq_create(sh->ctx, &sh->aso_age_mng->aso_sq, 0,
>  				  sh->tx_uar, sh->pdn, sh->eqn,
> -				  MLX5_ASO_QUEUE_LOG_DESC);
> +				  MLX5_ASO_QUEUE_LOG_DESC, sh->sq_ts_format);
>  }
> 
>  /**
> diff --git a/drivers/net/mlx5/mlx5_txpp.c b/drivers/net/mlx5/mlx5_txpp.c index 28afda28cb..72b0690913 100644
> --- a/drivers/net/mlx5/mlx5_txpp.c
> +++ b/drivers/net/mlx5/mlx5_txpp.c
> @@ -328,6 +328,7 @@ mlx5_txpp_create_rearm_queue(struct mlx5_dev_ctx_shared *sh)
>  	sq_attr.tis_num = sh->tis->id;
>  	sq_attr.cqn = wq->cq->id;
>  	sq_attr.cd_master = 1;
> +	sq_attr.ts_format = mlx5_ts_format_conv(sh->sq_ts_format);
>  	sq_attr.wq_attr.uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar);
>  	sq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
>  	sq_attr.wq_attr.pd = sh->pdn;
> @@ -577,6 +578,7 @@ mlx5_txpp_create_clock_queue(struct mlx5_dev_ctx_shared *sh)
>  	sq_attr.state = MLX5_SQC_STATE_RST;
>  	sq_attr.cqn = wq->cq->id;
>  	sq_attr.packet_pacing_rate_limit_index = sh->txpp.pp_id;
> +	sq_attr.ts_format = mlx5_ts_format_conv(sh->sq_ts_format);
>  	sq_attr.wq_attr.cd_slave = 1;
>  	sq_attr.wq_attr.uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar);
>  	sq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
> --
> 2.18.1


      reply	other threads:[~2021-05-31 11:33 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-19 18:50 Viacheslav Ovsiienko
2021-05-31 11:33 ` Xueming(Steven) Li [this message]

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