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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM4PR12MB5373.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 52e2a064-a489-446a-4e70-08da59a0665e X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Jun 2022 07:24:27.2973 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: KqFl9JZbTl8QRMYC3Uk+cPSpFrKLDvoKTRCGPg+9ITI36+tVXC1bv82JZquBTUAse7xz+szD27oO8uR2rssnsA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6059 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hey Michael, Applied, thanks! > -----Original Message----- > From: Michael Baum > Sent: Tuesday, June 28, 2022 11:34 PM > To: stable@dpdk.org > Cc: Matan Azrad ; Slava Ovsiienko ; Xueming(Steven) Li > Subject: [PATCH 20.11 v2] net/mlx5: fix LRO validation in Rx setup >=20 > [ upstream commit a213b8682117711c8e92475c5bbb321a3d8428dd ] >=20 > The mlx5_rx_queue_setup() get LRO offload from user. >=20 > When LRO is configured, the LRO flag in rxq_data is set to 1. >=20 > This patch adds validation to make sure the LRO is supported. >=20 > Fixes: 17ed314 ("net/mlx5: allow LRO per Rx queue") >=20 > Signed-off-by: Michael Baum > Acked-by: Matan Azrad > --- >=20 > v2: fix compilation issue. >=20 > drivers/net/mlx5/mlx5_rxq.c | 13 ++++++++++--- > 1 file changed, 10 insertions(+), 3 deletions(-) >=20 > diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c in= dex 4a263a5803..cb743a773c 100644 > --- a/drivers/net/mlx5/mlx5_rxq.c > +++ b/drivers/net/mlx5/mlx5_rxq.c > @@ -754,8 +754,18 @@ mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_= t idx, uint16_t desc, > (struct rte_eth_rxseg_split *)conf->rx_seg; > struct rte_eth_rxseg_split rx_single =3D {.mp =3D mp}; > uint16_t n_seg =3D conf->rx_nseg; > + uint64_t offloads =3D conf->offloads | > + dev->data->dev_conf.rxmode.offloads; > int res; >=20 > + if ((offloads & DEV_RX_OFFLOAD_TCP_LRO) && > + !priv->config.lro.supported) { > + DRV_LOG(ERR, > + "Port %u queue %u LRO is configured but not supported.", > + dev->data->port_id, idx); > + rte_errno =3D EINVAL; > + return -rte_errno; > + } > if (mp) { > /* > * The parameters should be checked on rte_eth_dev layer. > @@ -766,9 +776,6 @@ mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t= idx, uint16_t desc, > n_seg =3D 1; > } > if (n_seg > 1) { > - uint64_t offloads =3D conf->offloads | > - dev->data->dev_conf.rxmode.offloads; > - > /* The offloads should be checked on rte_eth_dev layer. */ > MLX5_ASSERT(offloads & DEV_RX_OFFLOAD_SCATTER); > if (!(offloads & RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT)) { > -- > 2.25.1