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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR12MB3753.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: d77f0cb0-c49a-48e4-c768-08d93d31283f X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Jul 2021 08:12:38.6546 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: bz5V+pmMV4VI5ZbPX2I+Bhu+UCh7SufIOdjJ0wSRrvYDCt2E2Nm2fI/gLozYsNkcG8GAhG07CbEpsQC+SBcddQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1228 Subject: Re: [dpdk-stable] [PATCH 1/2] net/mlx5: remove redundant operations X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, Ruifeng > -----Original Message----- > From: Ruifeng Wang > Sent: Tuesday, June 1, 2021 11:31 > To: Raslan Darawsheh ; Matan Azrad > ; Shahaf Shuler ; Slava Ovsiienko > > Cc: dev@dpdk.org; jerinj@marvell.com; nd@arm.com; > honnappa.nagarahalli@arm.com; Ruifeng Wang ; > stable@dpdk.org > Subject: [PATCH 1/2] net/mlx5: remove redundant operations >=20 > Some operations on mask are redundant and can be removed. > The change yielded 1.6% performance gain on N1SDP. > On ThunderX2, slight performance uplift was also observed. >=20 > Fixes: 570acdb1da8a ("net/mlx5: add vectorized Rx/Tx burst for ARM") > Cc: stable@dpdk.org >=20 > Signed-off-by: Ruifeng Wang > --- > drivers/net/mlx5/mlx5_rxtx_vec_neon.h | 9 +-------- > 1 file changed, 1 insertion(+), 8 deletions(-) >=20 > diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h > b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h > index 2234fbe6b2..98a75b09c6 100644 > --- a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h > +++ b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h > @@ -768,18 +768,11 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, > volatile struct mlx5_cqe *cq, > comp_mask), 0)) / > (sizeof(uint16_t) * 8); > /* D.6 mask out entries after the compressed CQE. */ > - mask =3D vcreate_u16(comp_idx < > MLX5_VPMD_DESCS_PER_LOOP ? > - -1UL >> (comp_idx * sizeof(uint16_t) * 8) : > - 0); > - invalid_mask =3D vorr_u16(invalid_mask, mask); > + invalid_mask =3D vorr_u16(invalid_mask, comp_mask); Mmmm... I'm not sure we can drop the masking compressed (and following) CQE= skip. Let's consider the completion scenario (the series of 4 CQEs, each element = is 64B long) 0: normal uncompressed CQE, ownership OK, format uncompressed, opcode OK, n= o error 1: compressed CQE, ownership OK, format compressed, opcode OK, no error 2: miniCQE array, format can be any!!, may be discovered as ownership OK, f= ormat uncompressed, opcode OK, no error 3: miniCQE array, format can be any!!, may be discovered as ownership OK, f= ormat uncompressed, opcode OK, no error Obviously, we should unconditionally mask out 2 and 3, regardless of recogn= ized their formats/opcode/error/etc. I think we can get the diff above and skip diff below: > /* D.7 count non-compressed valid CQEs. */ > n =3D __builtin_clzl(vget_lane_u64(vreinterpret_u64_u16( > invalid_mask), 0)) / (sizeof(uint16_t) * 8); > nocmp_n +=3D n; > - /* D.2 get the final invalid mask. */ > - mask =3D vcreate_u16(n < MLX5_VPMD_DESCS_PER_LOOP ? > - -1UL >> (n * sizeof(uint16_t) * 8) : 0); > - invalid_mask =3D vorr_u16(invalid_mask, mask); and get the correct final invalid_mask - all compressed and invalid CQEs an= d following ones will be masked out. With best regards, Slava