patches for DPDK stable branches
 help / color / mirror / Atom feed
* [dpdk-stable] [PATCH v2 1/6] net/mlx5: check for a field size in modify field action
       [not found] <20210324150439.9247-1-akozyrev@nvidia.com>
@ 2021-03-24 15:04 ` Alexander Kozyrev
  2021-03-30  7:09   ` Slava Ovsiienko
  2021-03-24 15:04 ` [dpdk-stable] [PATCH v2 2/6] net/mlx5: adjust modify field action endianess Alexander Kozyrev
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 8+ messages in thread
From: Alexander Kozyrev @ 2021-03-24 15:04 UTC (permalink / raw)
  To: dev; +Cc: rasland, viacheslavo, matan, orika, stable

Add a validation check to make sure that the specified width
for MODIFY_FIELD RTE action is not bigger than a field size.

Fixes: 641dbe4fb0 ("net/mlx5: support modify field flow action")
Cc: stable@dpdk.org

Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow_dv.c | 23 ++++++++++++++++-------
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 23e5849783..84e1bb6892 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -4608,9 +4608,22 @@ flow_dv_validate_action_modify_field(const uint64_t action_flags,
 	if (ret)
 		return ret;
 
+	if (action_modify_field->width == 0)
+		return rte_flow_error_set(error, EINVAL,
+					RTE_FLOW_ERROR_TYPE_ACTION,
+					NULL,
+					"no bits are requested to be modified");
+	else if (action_modify_field->width > dst_width ||
+		 action_modify_field->width > src_width)
+		return rte_flow_error_set(error, EINVAL,
+					RTE_FLOW_ERROR_TYPE_ACTION,
+					NULL,
+					"cannot modify more bits than"
+					" the width of a field");
 	if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
 	    action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
-		if (action_modify_field->dst.offset >= dst_width ||
+		if ((action_modify_field->dst.offset +
+		     action_modify_field->width > dst_width) ||
 		    (action_modify_field->dst.offset % 32))
 			return rte_flow_error_set(error, EINVAL,
 						RTE_FLOW_ERROR_TYPE_ACTION,
@@ -4626,7 +4639,8 @@ flow_dv_validate_action_modify_field(const uint64_t action_flags,
 	}
 	if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
 	    action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
-		if (action_modify_field->src.offset >= src_width ||
+		if ((action_modify_field->src.offset +
+		     action_modify_field->width > src_width) ||
 		    (action_modify_field->src.offset % 32))
 			return rte_flow_error_set(error, EINVAL,
 						RTE_FLOW_ERROR_TYPE_ACTION,
@@ -4640,11 +4654,6 @@ flow_dv_validate_action_modify_field(const uint64_t action_flags,
 						NULL,
 						"cannot copy from inner headers");
 	}
-	if (action_modify_field->width == 0)
-		return rte_flow_error_set(error, EINVAL,
-						RTE_FLOW_ERROR_TYPE_ACTION,
-						NULL,
-						"width is required for modify action");
 	if (action_modify_field->dst.field ==
 	    action_modify_field->src.field)
 		return rte_flow_error_set(error, EINVAL,
-- 
2.24.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [dpdk-stable] [PATCH v2 2/6] net/mlx5: adjust modify field action endianess
       [not found] <20210324150439.9247-1-akozyrev@nvidia.com>
  2021-03-24 15:04 ` [dpdk-stable] [PATCH v2 1/6] net/mlx5: check for a field size in modify field action Alexander Kozyrev
@ 2021-03-24 15:04 ` Alexander Kozyrev
  2021-03-30  7:09   ` Slava Ovsiienko
  2021-03-24 15:04 ` [dpdk-stable] [PATCH v2 3/6] net/mlx5: check extended metadata for mark modififcation Alexander Kozyrev
  2021-03-24 15:04 ` [dpdk-stable] [PATCH v2 6/6] net/mlx5: reject VXLAN ID's modifications Alexander Kozyrev
  3 siblings, 1 reply; 8+ messages in thread
From: Alexander Kozyrev @ 2021-03-24 15:04 UTC (permalink / raw)
  To: dev; +Cc: rasland, viacheslavo, matan, orika, stable

Masks that used to modify a packet field must be in a big
endian format. Convert then to BE to ensure proper modification.

Fixes: 641dbe4fb0 ("net/mlx5: support modify field flow action")
Cc: stable@dpdk.org

Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow_dv.c | 241 ++++++++++++++------------------
 1 file changed, 103 insertions(+), 138 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 84e1bb6892..a1e4e2e5df 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -1345,11 +1345,13 @@ mlx5_flow_field_id_to_modify_info
 			if (data->offset < 32) {
 				info[idx] = (struct field_modify_info){4, 0,
 						MLX5_MODI_OUT_DMAC_47_16};
-				mask[idx] = 0xffffffff;
 				if (width < 32) {
-					mask[idx] = mask[idx] << (32 - width);
+					mask[idx] =
+						rte_cpu_to_be_32(0xffffffff >>
+								 (32 - width));
 					width = 0;
 				} else {
+					mask[idx] = RTE_BE32(0xffffffff);
 					width -= 32;
 				}
 				if (!width)
@@ -1358,10 +1360,8 @@ mlx5_flow_field_id_to_modify_info
 			}
 			info[idx] = (struct field_modify_info){2, 4 * idx,
 						MLX5_MODI_OUT_DMAC_15_0};
-			mask[idx] = (width) ? 0x0000ffff : 0x0;
-			if (width < 16)
-				mask[idx] = (mask[idx] << (16 - width)) &
-						0x0000ffff;
+			mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
+						     (16 - width));
 		} else {
 			if (data->offset < 32)
 				info[idx++] = (struct field_modify_info){4, 0,
@@ -1375,11 +1375,13 @@ mlx5_flow_field_id_to_modify_info
 			if (data->offset < 32) {
 				info[idx] = (struct field_modify_info){4, 0,
 						MLX5_MODI_OUT_SMAC_47_16};
-				mask[idx] = 0xffffffff;
 				if (width < 32) {
-					mask[idx] = mask[idx] << (32 - width);
+					mask[idx] =
+						rte_cpu_to_be_32(0xffffffff >>
+								(32 - width));
 					width = 0;
 				} else {
+					mask[idx] = RTE_BE32(0xffffffff);
 					width -= 32;
 				}
 				if (!width)
@@ -1388,10 +1390,8 @@ mlx5_flow_field_id_to_modify_info
 			}
 			info[idx] = (struct field_modify_info){2, 4 * idx,
 						MLX5_MODI_OUT_SMAC_15_0};
-			mask[idx] = (width) ? 0x0000ffff : 0x0;
-			if (width < 16)
-				mask[idx] = (mask[idx] << (16 - width)) &
-						0x0000ffff;
+			mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
+						     (16 - width));
 		} else {
 			if (data->offset < 32)
 				info[idx++] = (struct field_modify_info){4, 0,
@@ -1406,91 +1406,71 @@ mlx5_flow_field_id_to_modify_info
 	case RTE_FLOW_FIELD_VLAN_ID:
 		info[idx] = (struct field_modify_info){2, 0,
 					MLX5_MODI_OUT_FIRST_VID};
-		if (mask) {
-			mask[idx] = 0x00000fff;
-			if (width < 12)
-				mask[idx] = (mask[idx] << (12 - width)) &
-						0x00000fff;
-		}
+		if (mask)
+			mask[idx] = rte_cpu_to_be_32(0x00000fff >>
+						     (12 - width));
 		break;
 	case RTE_FLOW_FIELD_MAC_TYPE:
 		info[idx] = (struct field_modify_info){2, 0,
 					MLX5_MODI_OUT_ETHERTYPE};
-		if (mask) {
-			mask[idx] = 0x0000ffff;
-			if (width < 16)
-				mask[idx] = (mask[idx] << (16 - width)) &
-						0x0000ffff;
-		}
+		if (mask)
+			mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
+						     (16 - width));
 		break;
 	case RTE_FLOW_FIELD_IPV4_DSCP:
 		info[idx] = (struct field_modify_info){1, 0,
 					MLX5_MODI_OUT_IP_DSCP};
-		if (mask) {
-			mask[idx] = 0x0000003f;
-			if (width < 6)
-				mask[idx] = (mask[idx] << (6 - width)) &
-						0x0000003f;
-		}
+		if (mask)
+			mask[idx] = rte_cpu_to_be_32(0x0000003f >>
+						     (6 - width));
 		break;
 	case RTE_FLOW_FIELD_IPV4_TTL:
 		info[idx] = (struct field_modify_info){1, 0,
 					MLX5_MODI_OUT_IPV4_TTL};
-		if (mask) {
-			mask[idx] = 0x000000ff;
-			if (width < 8)
-				mask[idx] = (mask[idx] << (8 - width)) &
-						0x000000ff;
-		}
+		if (mask)
+			mask[idx] = rte_cpu_to_be_32(0x000000ff >>
+						     (8 - width));
 		break;
 	case RTE_FLOW_FIELD_IPV4_SRC:
 		info[idx] = (struct field_modify_info){4, 0,
 					MLX5_MODI_OUT_SIPV4};
-		if (mask) {
-			mask[idx] = 0xffffffff;
-			if (width < 32)
-				mask[idx] = mask[idx] << (32 - width);
-		}
+		if (mask)
+			mask[idx] = rte_cpu_to_be_32(0xffffffff >>
+						     (32 - width));
 		break;
 	case RTE_FLOW_FIELD_IPV4_DST:
 		info[idx] = (struct field_modify_info){4, 0,
 					MLX5_MODI_OUT_DIPV4};
-		if (mask) {
-			mask[idx] = 0xffffffff;
-			if (width < 32)
-				mask[idx] = mask[idx] << (32 - width);
-		}
+		if (mask)
+			mask[idx] = rte_cpu_to_be_32(0xffffffff >>
+						     (32 - width));
 		break;
 	case RTE_FLOW_FIELD_IPV6_DSCP:
 		info[idx] = (struct field_modify_info){1, 0,
 					MLX5_MODI_OUT_IP_DSCP};
-		if (mask) {
-			mask[idx] = 0x0000003f;
-			if (width < 6)
-				mask[idx] = (mask[idx] << (6 - width)) &
-						0x0000003f;
-		}
+		if (mask)
+			mask[idx] = rte_cpu_to_be_32(0x0000003f >>
+						     (6 - width));
 		break;
 	case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
 		info[idx] = (struct field_modify_info){1, 0,
 					MLX5_MODI_OUT_IPV6_HOPLIMIT};
-		if (mask) {
-			mask[idx] = 0x000000ff;
-			if (width < 8)
-				mask[idx] = (mask[idx] << (8 - width)) &
-						0x000000ff;
-		}
+		if (mask)
+			mask[idx] = rte_cpu_to_be_32(0x000000ff >>
+						     (8 - width));
 		break;
 	case RTE_FLOW_FIELD_IPV6_SRC:
 		if (mask) {
 			if (data->offset < 32) {
 				info[idx] = (struct field_modify_info){4, 0,
 						MLX5_MODI_OUT_SIPV6_127_96};
-				mask[idx] = 0xffffffff;
 				if (width < 32) {
-					mask[idx] = mask[idx] << (32 - width);
+					mask[idx] =
+						rte_cpu_to_be_32(0xffffffff >>
+								 (32 - width));
 					width = 0;
 				} else {
+					mask[idx] = RTE_BE32(0xffffffff);
 					width -= 32;
 				}
 				if (!width)
@@ -1501,11 +1481,13 @@ mlx5_flow_field_id_to_modify_info
 				info[idx] = (struct field_modify_info){4,
 						4 * idx,
 						MLX5_MODI_OUT_SIPV6_95_64};
-				mask[idx] = 0xffffffff;
 				if (width < 32) {
-					mask[idx] = mask[idx] << (32 - width);
+					mask[idx] =
+						rte_cpu_to_be_32(0xffffffff >>
+								 (32 - width));
 					width = 0;
 				} else {
+					mask[idx] = RTE_BE32(0xffffffff);
 					width -= 32;
 				}
 				if (!width)
@@ -1516,11 +1498,13 @@ mlx5_flow_field_id_to_modify_info
 				info[idx] = (struct field_modify_info){4,
 						8 * idx,
 						MLX5_MODI_OUT_SIPV6_63_32};
-				mask[idx] = 0xffffffff;
 				if (width < 32) {
-					mask[idx] = mask[idx] << (32 - width);
+					mask[idx] =
+						rte_cpu_to_be_32(0xffffffff >>
+								 (32 - width));
 					width = 0;
 				} else {
+					mask[idx] = RTE_BE32(0xffffffff);
 					width -= 32;
 				}
 				if (!width)
@@ -1529,9 +1513,8 @@ mlx5_flow_field_id_to_modify_info
 			}
 			info[idx] = (struct field_modify_info){4, 12 * idx,
 						MLX5_MODI_OUT_SIPV6_31_0};
-			mask[idx] = 0xffffffff;
-			if (width < 32)
-				mask[idx] = mask[idx] << (32 - width);
+			mask[idx] = rte_cpu_to_be_32(0xffffffff >>
+						     (32 - width));
 		} else {
 			if (data->offset < 32)
 				info[idx++] = (struct field_modify_info){4, 0,
@@ -1552,11 +1535,13 @@ mlx5_flow_field_id_to_modify_info
 			if (data->offset < 32) {
 				info[idx] = (struct field_modify_info){4, 0,
 						MLX5_MODI_OUT_DIPV6_127_96};
-				mask[idx] = 0xffffffff;
 				if (width < 32) {
-					mask[idx] = mask[idx] << (32 - width);
+					mask[idx] =
+						rte_cpu_to_be_32(0xffffffff >>
+								 (32 - width));
 					width = 0;
 				} else {
+					mask[idx] = RTE_BE32(0xffffffff);
 					width -= 32;
 				}
 				if (!width)
@@ -1567,11 +1552,13 @@ mlx5_flow_field_id_to_modify_info
 				info[idx] = (struct field_modify_info){4,
 						4 * idx,
 						MLX5_MODI_OUT_DIPV6_95_64};
-				mask[idx] = 0xffffffff;
 				if (width < 32) {
-					mask[idx] = mask[idx] << (32 - width);
+					mask[idx] =
+						rte_cpu_to_be_32(0xffffffff >>
+								 (32 - width));
 					width = 0;
 				} else {
+					mask[idx] = RTE_BE32(0xffffffff);
 					width -= 32;
 				}
 				if (!width)
@@ -1582,11 +1569,13 @@ mlx5_flow_field_id_to_modify_info
 				info[idx] = (struct field_modify_info){4,
 						8 * idx,
 						MLX5_MODI_OUT_DIPV6_63_32};
-				mask[idx] = 0xffffffff;
 				if (width < 32) {
-					mask[idx] = mask[idx] << (32 - width);
+					mask[idx] =
+						rte_cpu_to_be_32(0xffffffff >>
+								 (32 - width));
 					width = 0;
 				} else {
+					mask[idx] = RTE_BE32(0xffffffff);
 					width -= 32;
 				}
 				if (!width)
@@ -1595,9 +1584,8 @@ mlx5_flow_field_id_to_modify_info
 			}
 			info[idx] = (struct field_modify_info){4, 12 * idx,
 						MLX5_MODI_OUT_DIPV6_31_0};
-			mask[idx] = 0xffffffff;
-			if (width < 32)
-				mask[idx] = mask[idx] << (32 - width);
+			mask[idx] = rte_cpu_to_be_32(0xffffffff >>
+						     (32 - width));
 		} else {
 			if (data->offset < 32)
 				info[idx++] = (struct field_modify_info){4, 0,
@@ -1616,70 +1604,51 @@ mlx5_flow_field_id_to_modify_info
 	case RTE_FLOW_FIELD_TCP_PORT_SRC:
 		info[idx] = (struct field_modify_info){2, 0,
 					MLX5_MODI_OUT_TCP_SPORT};
-		if (mask) {
-			mask[idx] = 0x0000ffff;
-			if (width < 16)
-				mask[idx] = (mask[idx] << (16 - width)) &
-						0x0000ffff;
-		}
+		if (mask)
+			mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
+						     (16 - width));
 		break;
 	case RTE_FLOW_FIELD_TCP_PORT_DST:
 		info[idx] = (struct field_modify_info){2, 0,
 					MLX5_MODI_OUT_TCP_DPORT};
-		if (mask) {
-			mask[idx] = 0x0000ffff;
-			if (width < 16)
-				mask[idx] = (mask[idx] << (16 - width)) &
-						0x0000ffff;
-		}
+		if (mask)
+			mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
+						     (16 - width));
 		break;
 	case RTE_FLOW_FIELD_TCP_SEQ_NUM:
 		info[idx] = (struct field_modify_info){4, 0,
 					MLX5_MODI_OUT_TCP_SEQ_NUM};
-		if (mask) {
-			mask[idx] = 0xffffffff;
-			if (width < 32)
-				mask[idx] = (mask[idx] << (32 - width));
-		}
+		if (mask)
+			mask[idx] = rte_cpu_to_be_32(0xffffffff >>
+						     (32 - width));
 		break;
 	case RTE_FLOW_FIELD_TCP_ACK_NUM:
 		info[idx] = (struct field_modify_info){4, 0,
 					MLX5_MODI_OUT_TCP_ACK_NUM};
-		if (mask) {
-			mask[idx] = 0xffffffff;
-			if (width < 32)
-				mask[idx] = (mask[idx] << (32 - width));
-		}
+		if (mask)
+			mask[idx] = rte_cpu_to_be_32(0xffffffff >>
+						     (32 - width));
 		break;
 	case RTE_FLOW_FIELD_TCP_FLAGS:
 		info[idx] = (struct field_modify_info){1, 0,
 					MLX5_MODI_OUT_TCP_FLAGS};
-		if (mask) {
-			mask[idx] = 0x0000003f;
-			if (width < 6)
-				mask[idx] = (mask[idx] << (6 - width)) &
-						0x0000003f;
-		}
+		if (mask)
+			mask[idx] = rte_cpu_to_be_32(0x0000003f >>
+						     (6 - width));
 		break;
 	case RTE_FLOW_FIELD_UDP_PORT_SRC:
 		info[idx] = (struct field_modify_info){2, 0,
 					MLX5_MODI_OUT_UDP_SPORT};
-		if (mask) {
-			mask[idx] = 0x0000ffff;
-			if (width < 16)
-				mask[idx] = (mask[idx] << (16 - width)) &
-						0x0000ffff;
-		}
+		if (mask)
+			mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
+						     (16 - width));
 		break;
 	case RTE_FLOW_FIELD_UDP_PORT_DST:
 		info[idx] = (struct field_modify_info){2, 0,
 					MLX5_MODI_OUT_UDP_DPORT};
-		if (mask) {
-			mask[idx] = 0x0000ffff;
-			if (width < 16)
-				mask[idx] = (mask[idx] << (16 - width)) &
-						0x0000ffff;
-		}
+		if (mask)
+			mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
+						     (16 - width));
 		break;
 	case RTE_FLOW_FIELD_VXLAN_VNI:
 		/* not supported yet */
@@ -1690,11 +1659,9 @@ mlx5_flow_field_id_to_modify_info
 	case RTE_FLOW_FIELD_GTP_TEID:
 		info[idx] = (struct field_modify_info){4, 0,
 					MLX5_MODI_GTP_TEID};
-		if (mask) {
-			mask[idx] = 0xffffffff;
-			if (width < 32)
-				mask[idx] = mask[idx] << (32 - width);
-		}
+		if (mask)
+			mask[idx] = rte_cpu_to_be_32(0xffffffff >>
+						     (32 - width));
 		break;
 	case RTE_FLOW_FIELD_TAG:
 		{
@@ -1706,11 +1673,10 @@ mlx5_flow_field_id_to_modify_info
 			MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
 			info[idx] = (struct field_modify_info){4, 0,
 						reg_to_field[reg]};
-			if (mask) {
-				mask[idx] = 0xffffffff;
-				if (width < 32)
-					mask[idx] = mask[idx] << (32 - width);
-			}
+			if (mask)
+				mask[idx] =
+					rte_cpu_to_be_32(0xffffffff >>
+							 (32 - width));
 		}
 		break;
 	case RTE_FLOW_FIELD_MARK:
@@ -1723,11 +1689,10 @@ mlx5_flow_field_id_to_modify_info
 			MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
 			info[idx] = (struct field_modify_info){4, 0,
 						reg_to_field[reg]};
-			if (mask) {
-				mask[idx] = 0xffffffff;
-				if (width < 32)
-					mask[idx] = mask[idx] << (32 - width);
-			}
+			if (mask)
+				mask[idx] =
+					rte_cpu_to_be_32(0xffffffff >>
+							 (32 - width));
 		}
 		break;
 	case RTE_FLOW_FIELD_META:
@@ -1739,11 +1704,10 @@ mlx5_flow_field_id_to_modify_info
 			MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
 			info[idx] = (struct field_modify_info){4, 0,
 						reg_to_field[reg]};
-			if (mask) {
-				mask[idx] = 0xffffffff;
-				if (width < 32)
-					mask[idx] = mask[idx] << (32 - width);
-			}
+			if (mask)
+				mask[idx] =
+					rte_cpu_to_be_32(0xffffffff >>
+							 (32 - width));
 		}
 		break;
 	case RTE_FLOW_FIELD_POINTER:
@@ -1751,7 +1715,7 @@ mlx5_flow_field_id_to_modify_info
 			if (mask[idx]) {
 				memcpy(&value[idx],
 					(void *)(uintptr_t)data->value, 32);
-				value[idx] = RTE_BE32(value[idx]);
+				value[idx] = rte_cpu_to_be_32(value[idx]);
 				break;
 			}
 		}
@@ -1759,7 +1723,8 @@ mlx5_flow_field_id_to_modify_info
 	case RTE_FLOW_FIELD_VALUE:
 		for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
 			if (mask[idx]) {
-				value[idx] = RTE_BE32((uint32_t)data->value);
+				value[idx] =
+					rte_cpu_to_be_32((uint32_t)data->value);
 				break;
 			}
 		}
-- 
2.24.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [dpdk-stable] [PATCH v2 3/6] net/mlx5: check extended metadata for mark modififcation
       [not found] <20210324150439.9247-1-akozyrev@nvidia.com>
  2021-03-24 15:04 ` [dpdk-stable] [PATCH v2 1/6] net/mlx5: check for a field size in modify field action Alexander Kozyrev
  2021-03-24 15:04 ` [dpdk-stable] [PATCH v2 2/6] net/mlx5: adjust modify field action endianess Alexander Kozyrev
@ 2021-03-24 15:04 ` Alexander Kozyrev
  2021-03-30  7:09   ` Slava Ovsiienko
  2021-03-24 15:04 ` [dpdk-stable] [PATCH v2 6/6] net/mlx5: reject VXLAN ID's modifications Alexander Kozyrev
  3 siblings, 1 reply; 8+ messages in thread
From: Alexander Kozyrev @ 2021-03-24 15:04 UTC (permalink / raw)
  To: dev; +Cc: rasland, viacheslavo, matan, orika, stable

The MODIFY_FIELD RTE action requires the extended metadata support
in order to manipulate on MARK register. Check if it is supported
and reject the MODIFY_FIELD action if it is not.

Fixes: 641dbe4fb0 ("net/mlx5: support modify field flow action")
Cc: stable@dpdk.org

Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow_dv.c | 24 +++++++++++++++++++-----
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index a1e4e2e5df..f2bc3162c1 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -4542,7 +4542,8 @@ mlx5_flow_item_field_width(enum rte_flow_field_id field)
 
 /**
  * Validate the generic modify field actions.
- *
+ * @param[in] dev
+ *   Pointer to the rte_eth_dev structure.
  * @param[in] action_flags
  *   Holds the actions detected until now.
  * @param[in] action
@@ -4557,11 +4558,14 @@ mlx5_flow_item_field_width(enum rte_flow_field_id field)
  *   a negative errno value otherwise and rte_errno is set.
  */
 static int
-flow_dv_validate_action_modify_field(const uint64_t action_flags,
+flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
+				   const uint64_t action_flags,
 				   const struct rte_flow_action *action,
 				   struct rte_flow_error *error)
 {
 	int ret = 0;
+	struct mlx5_priv *priv = dev->data->dev_private;
+	struct mlx5_dev_config *config = &priv->config;
 	const struct rte_flow_action_modify_field *action_modify_field =
 		action->conf;
 	uint32_t dst_width =
@@ -4640,6 +4644,15 @@ flow_dv_validate_action_modify_field(const uint64_t action_flags,
 				NULL,
 				"modifications of an arbitrary"
 				" place in a packet is not supported");
+	if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
+	    action_modify_field->src.field == RTE_FLOW_FIELD_MARK) {
+		if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
+		    !mlx5_flow_ext_mreg_supported(dev))
+			return rte_flow_error_set(error, ENOTSUP,
+					RTE_FLOW_ERROR_TYPE_ACTION, action,
+					"cannot modify mark without extended"
+					" metadata register support");
+	}
 	if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
 		return rte_flow_error_set(error, EINVAL,
 				RTE_FLOW_ERROR_TYPE_ACTION,
@@ -6914,9 +6927,10 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
 						RTE_FLOW_ERROR_TYPE_ACTION,
 						NULL, "modify field action "
 						"is not supported for group 0");
-			ret = flow_dv_validate_action_modify_field(action_flags,
-								 actions,
-								 error);
+			ret = flow_dv_validate_action_modify_field(dev,
+								   action_flags,
+								   actions,
+								   error);
 			if (ret < 0)
 				return ret;
 			/* Count all modify-header actions as one action. */
-- 
2.24.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [dpdk-stable] [PATCH v2 6/6] net/mlx5: reject VXLAN ID's modifications
       [not found] <20210324150439.9247-1-akozyrev@nvidia.com>
                   ` (2 preceding siblings ...)
  2021-03-24 15:04 ` [dpdk-stable] [PATCH v2 3/6] net/mlx5: check extended metadata for mark modififcation Alexander Kozyrev
@ 2021-03-24 15:04 ` Alexander Kozyrev
  2021-03-30  7:10   ` Slava Ovsiienko
  3 siblings, 1 reply; 8+ messages in thread
From: Alexander Kozyrev @ 2021-03-24 15:04 UTC (permalink / raw)
  To: dev; +Cc: rasland, viacheslavo, matan, orika, stable

Modification of the 802.1Q Tag Identificator, VXLAN Network
Identificator or GENEVE Network Identificator is not supported.
Reject attempt to modify these fields via the MODIFY_FIELD
action and document this mlx5 driver limitation.

Fixes: 641dbe4fb0 ("net/mlx5: support modify field flow action")
Cc: stable@dpdk.org

Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
---
 doc/guides/nics/mlx5.rst        |  1 +
 drivers/net/mlx5/mlx5_flow_dv.c | 21 +++++++++++++++++++++
 2 files changed, 22 insertions(+)

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index a2cfc51b2a..92369fa5ee 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -383,6 +383,7 @@ Limitations
 
   - Supports the 'set' operation only for ``RTE_FLOW_ACTION_TYPE_MODIFY_FIELD`` action.
   - Modification of an arbitrary place in a packet via the special ``RTE_FLOW_FIELD_START`` Field ID is not supported.
+  - Modification of the 802.1Q Tag, VXLAN Network or GENEVE Network ID's is not supported.
   - Encapsulation levels are not supported, can modify outermost header fields only.
   - Offsets must be 32-bits aligned, cannot skip past the boundary of a field.
 
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index ecabf63f53..223a7d0e36 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -4650,6 +4650,27 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
 				NULL,
 				"modifications of an arbitrary"
 				" place in a packet is not supported");
+	if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
+	    action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
+		return rte_flow_error_set(error, EINVAL,
+				RTE_FLOW_ERROR_TYPE_ACTION,
+				NULL,
+				"modifications of the 802.1Q Tag"
+				" Identifier is not supported");
+	if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
+	    action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
+		return rte_flow_error_set(error, EINVAL,
+				RTE_FLOW_ERROR_TYPE_ACTION,
+				NULL,
+				"modifications of the VXLAN Network"
+				" Identifier is not supported");
+	if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
+	    action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
+		return rte_flow_error_set(error, EINVAL,
+				RTE_FLOW_ERROR_TYPE_ACTION,
+				NULL,
+				"modifications of the GENEVE Network"
+				" Identifier is not supported");
 	if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
 	    action_modify_field->src.field == RTE_FLOW_FIELD_MARK) {
 		if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
-- 
2.24.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [dpdk-stable] [PATCH v2 1/6] net/mlx5: check for a field size in modify field action
  2021-03-24 15:04 ` [dpdk-stable] [PATCH v2 1/6] net/mlx5: check for a field size in modify field action Alexander Kozyrev
@ 2021-03-30  7:09   ` Slava Ovsiienko
  0 siblings, 0 replies; 8+ messages in thread
From: Slava Ovsiienko @ 2021-03-30  7:09 UTC (permalink / raw)
  To: Alexander Kozyrev, dev; +Cc: Raslan Darawsheh, Matan Azrad, Ori Kam, stable

> -----Original Message-----
> From: Alexander Kozyrev <akozyrev@nvidia.com>
> Sent: Wednesday, March 24, 2021 17:05
> To: dev@dpdk.org
> Cc: Raslan Darawsheh <rasland@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com>; Ori Kam
> <orika@nvidia.com>; stable@dpdk.org
> Subject: [PATCH v2 1/6] net/mlx5: check for a field size in modify field action
> 
> Add a validation check to make sure that the specified width for
> MODIFY_FIELD RTE action is not bigger than a field size.
> 
> Fixes: 641dbe4fb0 ("net/mlx5: support modify field flow action")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [dpdk-stable] [PATCH v2 2/6] net/mlx5: adjust modify field action endianess
  2021-03-24 15:04 ` [dpdk-stable] [PATCH v2 2/6] net/mlx5: adjust modify field action endianess Alexander Kozyrev
@ 2021-03-30  7:09   ` Slava Ovsiienko
  0 siblings, 0 replies; 8+ messages in thread
From: Slava Ovsiienko @ 2021-03-30  7:09 UTC (permalink / raw)
  To: Alexander Kozyrev, dev; +Cc: Raslan Darawsheh, Matan Azrad, Ori Kam, stable

> -----Original Message-----
> From: Alexander Kozyrev <akozyrev@nvidia.com>
> Sent: Wednesday, March 24, 2021 17:05
> To: dev@dpdk.org
> Cc: Raslan Darawsheh <rasland@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com>; Ori Kam
> <orika@nvidia.com>; stable@dpdk.org
> Subject: [PATCH v2 2/6] net/mlx5: adjust modify field action endianess
> 
> Masks that used to modify a packet field must be in a big endian format.
> Convert then to BE to ensure proper modification.
> 
> Fixes: 641dbe4fb0 ("net/mlx5: support modify field flow action")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [dpdk-stable] [PATCH v2 3/6] net/mlx5: check extended metadata for mark modififcation
  2021-03-24 15:04 ` [dpdk-stable] [PATCH v2 3/6] net/mlx5: check extended metadata for mark modififcation Alexander Kozyrev
@ 2021-03-30  7:09   ` Slava Ovsiienko
  0 siblings, 0 replies; 8+ messages in thread
From: Slava Ovsiienko @ 2021-03-30  7:09 UTC (permalink / raw)
  To: Alexander Kozyrev, dev; +Cc: Raslan Darawsheh, Matan Azrad, Ori Kam, stable

> -----Original Message-----
> From: Alexander Kozyrev <akozyrev@nvidia.com>
> Sent: Wednesday, March 24, 2021 17:05
> To: dev@dpdk.org
> Cc: Raslan Darawsheh <rasland@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com>; Ori Kam
> <orika@nvidia.com>; stable@dpdk.org
> Subject: [PATCH v2 3/6] net/mlx5: check extended metadata for mark
> modififcation
> 
> The MODIFY_FIELD RTE action requires the extended metadata support in
> order to manipulate on MARK register. Check if it is supported and reject the
> MODIFY_FIELD action if it is not.
> 
> Fixes: 641dbe4fb0 ("net/mlx5: support modify field flow action")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [dpdk-stable] [PATCH v2 6/6] net/mlx5: reject VXLAN ID's modifications
  2021-03-24 15:04 ` [dpdk-stable] [PATCH v2 6/6] net/mlx5: reject VXLAN ID's modifications Alexander Kozyrev
@ 2021-03-30  7:10   ` Slava Ovsiienko
  0 siblings, 0 replies; 8+ messages in thread
From: Slava Ovsiienko @ 2021-03-30  7:10 UTC (permalink / raw)
  To: Alexander Kozyrev, dev; +Cc: Raslan Darawsheh, Matan Azrad, Ori Kam, stable

> -----Original Message-----
> From: Alexander Kozyrev <akozyrev@nvidia.com>
> Sent: Wednesday, March 24, 2021 17:05
> To: dev@dpdk.org
> Cc: Raslan Darawsheh <rasland@nvidia.com>; Slava Ovsiienko
> <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com>; Ori Kam
> <orika@nvidia.com>; stable@dpdk.org
> Subject: [PATCH v2 6/6] net/mlx5: reject VXLAN ID's modifications
> 
> Modification of the 802.1Q Tag Identificator, VXLAN Network Identificator or
> GENEVE Network Identificator is not supported.
> Reject attempt to modify these fields via the MODIFY_FIELD action and
> document this mlx5 driver limitation.
> 
> Fixes: 641dbe4fb0 ("net/mlx5: support modify field flow action")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

^ permalink raw reply	[flat|nested] 8+ messages in thread

end of thread, other threads:[~2021-03-30  7:10 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
     [not found] <20210324150439.9247-1-akozyrev@nvidia.com>
2021-03-24 15:04 ` [dpdk-stable] [PATCH v2 1/6] net/mlx5: check for a field size in modify field action Alexander Kozyrev
2021-03-30  7:09   ` Slava Ovsiienko
2021-03-24 15:04 ` [dpdk-stable] [PATCH v2 2/6] net/mlx5: adjust modify field action endianess Alexander Kozyrev
2021-03-30  7:09   ` Slava Ovsiienko
2021-03-24 15:04 ` [dpdk-stable] [PATCH v2 3/6] net/mlx5: check extended metadata for mark modififcation Alexander Kozyrev
2021-03-30  7:09   ` Slava Ovsiienko
2021-03-24 15:04 ` [dpdk-stable] [PATCH v2 6/6] net/mlx5: reject VXLAN ID's modifications Alexander Kozyrev
2021-03-30  7:10   ` Slava Ovsiienko

patches for DPDK stable branches

This inbox may be cloned and mirrored by anyone:

	git clone --mirror https://inbox.dpdk.org/stable/0 stable/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 stable stable/ https://inbox.dpdk.org/stable \
		stable@dpdk.org
	public-inbox-index stable

Example config snippet for mirrors.
Newsgroup available over NNTP:
	nntp://inbox.dpdk.org/inbox.dpdk.stable


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git