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Mon, 12 Apr 2021 08:27:30 +0000 Received: from DM6PR12MB3753.namprd12.prod.outlook.com ([fe80::20f7:11fc:9d46:9258]) by DM6PR12MB3753.namprd12.prod.outlook.com ([fe80::20f7:11fc:9d46:9258%6]) with mapi id 15.20.4020.022; Mon, 12 Apr 2021 08:27:30 +0000 From: Slava Ovsiienko To: Feifei Wang , Matan Azrad , Shahaf Shuler , Yongseok Koh CC: "dev@dpdk.org" , "nd@arm.com" , "stable@dpdk.org" , Ruifeng Wang Thread-Topic: [PATCH v1 3/4] net/mlx5: fix rebuild bug for Memory Region cache Thread-Index: AQHXG8cWFxZYWyFpJUm7yYF997hX4qqwqlRA Date: Mon, 12 Apr 2021 08:27:30 +0000 Message-ID: References: <20210318071840.359957-1-feifei.wang2@arm.com> <20210318071840.359957-4-feifei.wang2@arm.com> In-Reply-To: <20210318071840.359957-4-feifei.wang2@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: arm.com; dkim=none (message not signed) header.d=none;arm.com; dmarc=none action=none header.from=nvidia.com; x-originating-ip: [95.164.10.10] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 41e1e896-7c84-4a25-457d-08d8fd8cd063 x-ms-traffictypediagnostic: DM6PR12MB2921: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:7691; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR12MB3753.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 41e1e896-7c84-4a25-457d-08d8fd8cd063 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Apr 2021 08:27:30.5001 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: QihCT8fP9qP7kU/y22IPLD3VkUDUlvEeqIKzdSoBejNNesBI4mRe68kwMgoG4vcyQG5018sUvbGh3qurbEMLgQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2921 Subject: Re: [dpdk-stable] [PATCH v1 3/4] net/mlx5: fix rebuild bug for Memory Region cache X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, Feifei Sorry, I do not follow what this patch fixes. Do we have some issue/bug wit= h MR cache in practice? Each Tx queue has its own dedicated "local" cache for MRs to convert buffer= address in mbufs being transmitted to LKeys (HW-related entity handle) and the "global" cache for all MR regis= tered on the device. AFAIK, how conversion happens in datapath: - check the local queue cache flush request - lookup in local cache - if not found: - acquire lock for global cache read access - lookup in global cache - release lock for global cache How cache update on memory freeing/unregistering happens: - acquire lock for global cache write access=20 - [a] remove relevant MRs from the global cache - [b] set local caches flush request=20 - free global cache lock If I understand correctly, your patch swaps [a] and [b], and local caches flush is requested earlier. What problem does it solve? It is not supposed there are in datapath some mbufs referencing to the memory being freed. Application must ensure this and must not alloca= te new mbufs from this memory regions being freed. Hence, the lookups for thes= e MRs in caches should not occur. For other side, the cache flush has negative effect - the local cache is getting empty and can't provide translation for other valid (not being remo= ved) MRs, and the translation has to look up in the global cache, that is locked now for rebuilding, this causes the delays in datapatch on acquiring global cac= he lock. So, I see some potential performance impact.=20 With best regards, Slava > -----Original Message----- > From: Feifei Wang > Sent: Thursday, March 18, 2021 9:19 > To: Matan Azrad ; Shahaf Shuler > ; Slava Ovsiienko ; > Yongseok Koh > Cc: dev@dpdk.org; nd@arm.com; Feifei Wang ; > stable@dpdk.org; Ruifeng Wang > Subject: [PATCH v1 3/4] net/mlx5: fix rebuild bug for Memory Region cache >=20 > 'dev_gen' is a variable to inform other cores to flush their local cache = when > global cache is rebuilt. >=20 > However, if 'dev_gen' is updated after global cache is rebuilt, other cor= es > may load a wrong memory region lkey value from old local cache. >=20 > Timeslot main core worker core > 1 rebuild global cache > 2 load unchanged dev_gen > 3 update dev_gen > 4 look up old local cache >=20 > From the example above, we can see that though global cache is rebuilt, d= ue > to that dev_gen is not updated, the worker core may look up old cache tab= le > and receive a wrong memory region lkey value. >=20 > To fix this, updating 'dev_gen' should be moved before rebuilding global > cache to inform worker cores to flush their local cache when global cache > start rebuilding. And wmb can ensure the sequence of this process. >=20 > Fixes: 974f1e7ef146 ("net/mlx5: add new memory region support") > Cc: stable@dpdk.org >=20 > Suggested-by: Ruifeng Wang > Signed-off-by: Feifei Wang > Reviewed-by: Ruifeng Wang > --- > drivers/net/mlx5/mlx5_mr.c | 37 +++++++++++++++++-------------------- > 1 file changed, 17 insertions(+), 20 deletions(-) >=20 > diff --git a/drivers/net/mlx5/mlx5_mr.c b/drivers/net/mlx5/mlx5_mr.c inde= x > da4e91fc2..7ce1d3e64 100644 > --- a/drivers/net/mlx5/mlx5_mr.c > +++ b/drivers/net/mlx5/mlx5_mr.c > @@ -103,20 +103,18 @@ mlx5_mr_mem_event_free_cb(struct > mlx5_dev_ctx_shared *sh, > rebuild =3D 1; > } > if (rebuild) { > - mlx5_mr_rebuild_cache(&sh->share_cache); > + ++sh->share_cache.dev_gen; > + DEBUG("broadcasting local cache flush, gen=3D%d", > + sh->share_cache.dev_gen); > + > /* > * Flush local caches by propagating invalidation across cores. > - * rte_smp_wmb() is enough to synchronize this event. If > one of > - * freed memsegs is seen by other core, that means the > memseg > - * has been allocated by allocator, which will come after this > - * free call. Therefore, this store instruction (incrementing > - * generation below) will be guaranteed to be seen by other > core > - * before the core sees the newly allocated memory. > + * rte_smp_wmb() is to keep the order that dev_gen > updated before > + * rebuilding global cache. Therefore, other core can flush > their > + * local cache on time. > */ > - ++sh->share_cache.dev_gen; > - DEBUG("broadcasting local cache flush, gen=3D%d", > - sh->share_cache.dev_gen); > rte_smp_wmb(); > + mlx5_mr_rebuild_cache(&sh->share_cache); > } > rte_rwlock_write_unlock(&sh->share_cache.rwlock); > } > @@ -407,20 +405,19 @@ mlx5_dma_unmap(struct rte_pci_device *pdev, > void *addr, > mlx5_mr_free(mr, sh->share_cache.dereg_mr_cb); > DEBUG("port %u remove MR(%p) from list", dev->data->port_id, > (void *)mr); > - mlx5_mr_rebuild_cache(&sh->share_cache); > + > + ++sh->share_cache.dev_gen; > + DEBUG("broadcasting local cache flush, gen=3D%d", > + sh->share_cache.dev_gen); > + > /* > * Flush local caches by propagating invalidation across cores. > - * rte_smp_wmb() is enough to synchronize this event. If one of > - * freed memsegs is seen by other core, that means the memseg > - * has been allocated by allocator, which will come after this > - * free call. Therefore, this store instruction (incrementing > - * generation below) will be guaranteed to be seen by other core > - * before the core sees the newly allocated memory. > + * rte_smp_wmb() is to keep the order that dev_gen updated > before > + * rebuilding global cache. Therefore, other core can flush their > + * local cache on time. > */ > - ++sh->share_cache.dev_gen; > - DEBUG("broadcasting local cache flush, gen=3D%d", > - sh->share_cache.dev_gen); > rte_smp_wmb(); > + mlx5_mr_rebuild_cache(&sh->share_cache); > rte_rwlock_read_unlock(&sh->share_cache.rwlock); > return 0; > } > -- > 2.25.1