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Mon, 15 Mar 2021 17:38:40 +0000 From: "Coyle, David" To: "Lu, Wenzhuo" , "dev@dpdk.org" CC: "Lu, Wenzhuo" , "stable@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH 3/3] net/i40e: fix segment fault in AVX512 Thread-Index: AQHXFt8PgavoJrnoV0Svfo8KA8NH1aqFU5wg Date: Mon, 15 Mar 2021 17:38:40 +0000 Message-ID: References: <1615512441-17495-1-git-send-email-wenzhuo.lu@intel.com> In-Reply-To: <1615512441-17495-1-git-send-email-wenzhuo.lu@intel.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [109.78.96.244] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 0689c83f-39a6-4b58-d556-08d8e7d92bf5 x-ms-traffictypediagnostic: MN2PR11MB3728: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:2803; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN2PR11MB3550.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0689c83f-39a6-4b58-d556-08d8e7d92bf5 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Mar 2021 17:38:40.3026 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: oW9fkqZInimA6qoVbhb2x8B9nMXRxXNlJ7kb+bmDhR0NoJ37lKZuqgWbftUogP6tVb8wLw1sBXICGzTSOvz1cg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3728 X-OriginatorOrg: intel.com Subject: Re: [dpdk-stable] [dpdk-dev] [PATCH 3/3] net/i40e: fix segment fault in AVX512 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi Wenzhuo > -----Original Message----- > From: dev On Behalf Of Wenzhuo Lu > Sent: Friday, March 12, 2021 1:27 AM > To: dev@dpdk.org > Cc: Lu, Wenzhuo ; stable@dpdk.org > Subject: [dpdk-dev] [PATCH 3/3] net/i40e: fix segment fault in AVX512 >=20 > Fix segment fault when failing to get the memory from the pool. >=20 > Fixes: e6a6a138919f ("net/i40e: add AVX512 vector path") > Cc: stable@dpdk.org >=20 > Reported-by: David Coyle > Signed-off-by: Wenzhuo Lu > --- > drivers/net/i40e/i40e_rxtx_vec_avx512.c | 128 > ++++++++++++++++++++++++++++++++ > 1 file changed, 128 insertions(+) >=20 > diff --git a/drivers/net/i40e/i40e_rxtx_vec_avx512.c > b/drivers/net/i40e/i40e_rxtx_vec_avx512.c > index 862c916..36521da 100644 > --- a/drivers/net/i40e/i40e_rxtx_vec_avx512.c > +++ b/drivers/net/i40e/i40e_rxtx_vec_avx512.c > @@ -32,6 +32,9 @@ >=20 > rxdp =3D rxq->rx_ring + rxq->rxrearm_start; >=20 > + if (!cache) > + goto normal; [DC] Like in IAVF and ICE, should we also check for cache->len =3D=3D 0, li= ke is done in Tx path? > + > /* We need to pull 'n' more MBUFs into the software ring from > mempool > * We inline the mempool function here, so we can vectorize the > copy > * from the cache into the shadow ring. > @@ -132,7 +135,132 @@ > #endif > rxep +=3D 8, rxdp +=3D 8, cache->len -=3D 8; > } > + goto done; > + > +normal: > + /* Pull 'n' more MBUFs into the software ring */ > + if (rte_mempool_get_bulk(rxq->mp, > + (void *)rxep, > + RTE_I40E_RXQ_REARM_THRESH) < 0) { > + if (rxq->rxrearm_nb + RTE_I40E_RXQ_REARM_THRESH >=3D > + rxq->nb_rx_desc) { > + __m128i dma_addr0; > + > + dma_addr0 =3D _mm_setzero_si128(); > + for (i =3D 0; i < RTE_I40E_DESCS_PER_LOOP; i++) { > + rxep[i].mbuf =3D &rxq->fake_mbuf; > + _mm_store_si128((__m128i *)&rxdp[i].read, > + dma_addr0); > + } > + } > + rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed > +=3D > + RTE_I40E_RXQ_REARM_THRESH; > + return; > + } > + > +#ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC > + struct rte_mbuf *mb0, *mb1; > + __m128i dma_addr0, dma_addr1; > + __m128i hdr_room =3D _mm_set_epi64x(RTE_PKTMBUF_HEADROOM, > + RTE_PKTMBUF_HEADROOM); > + /* Initialize the mbufs in vector, process 4 mbufs in one loop */ [DC] Comment should say 2 mbufs > + for (i =3D 0; i < RTE_I40E_RXQ_REARM_THRESH; i +=3D 2, rxep +=3D 2) { > + __m128i vaddr0, vaddr1; > + > + mb0 =3D rxep[0].mbuf; > + mb1 =3D rxep[1].mbuf; > + > + /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */ > + RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=3D > + offsetof(struct rte_mbuf, buf_addr) + 8); > + vaddr0 =3D _mm_loadu_si128((__m128i *)&mb0->buf_addr); > + vaddr1 =3D _mm_loadu_si128((__m128i *)&mb1->buf_addr); > + > + /* convert pa to dma_addr hdr/data */ > + dma_addr0 =3D _mm_unpackhi_epi64(vaddr0, vaddr0); > + dma_addr1 =3D _mm_unpackhi_epi64(vaddr1, vaddr1); > + > + /* add headroom to pa values */ > + dma_addr0 =3D _mm_add_epi64(dma_addr0, hdr_room); > + dma_addr1 =3D _mm_add_epi64(dma_addr1, hdr_room); > + > + /* flush desc with pa dma_addr */ > + _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0); > + _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1); > + } > +#else > + struct rte_mbuf *mb0, *mb1, *mb2, *mb3; > + struct rte_mbuf *mb4, *mb5, *mb6, *mb7; > + __m512i dma_addr0_3, dma_addr4_7; > + __m512i hdr_room =3D > _mm512_set1_epi64(RTE_PKTMBUF_HEADROOM); > + /* Initialize the mbufs in vector, process 4 mbufs in one loop */ [DC] Comment should say 8 mbufs > + for (i =3D 0; i < RTE_I40E_RXQ_REARM_THRESH; > + i +=3D 8, rxep +=3D 8, rxdp +=3D 8) { > + __m128i vaddr0, vaddr1, vaddr2, vaddr3; > + __m128i vaddr4, vaddr5, vaddr6, vaddr7; > + vaddr6 =3D _mm_loadu_si128((__m128i *)&mb6->buf_addr); > + vaddr7 =3D _mm_loadu_si128((__m128i *)&mb7->buf_addr); > + > + /** > + * merge 0 & 1, by casting 0 to 256-bit and inserting 1 > + * into the high lanes. Similarly for 2 & 3 > + */ [DC] Comment should say "Similarly for 2 & 3, 4 & 5, 6 & 7" > + vaddr0_1 =3D > + > _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr0), > + vaddr1, 1); > + /* flush desc with pa dma_addr */ > + _mm512_store_si512((__m512i *)&rxdp->read, > dma_addr0_3); > + _mm512_store_si512((__m512i *)&(rxdp + 4)->read, > dma_addr4_7); > + } > +#endif [DC] Again, there's common code here with the avx2 file and also with the I= AVF and ICE PMDs. As I said in other reviews, maybe it's not practical to share code across P= MDs. But might be good to have some common functions within each PMD for avx2 an= d avx512 paths >=20 > +done: > rxq->rxrearm_start +=3D RTE_I40E_RXQ_REARM_THRESH; > if (rxq->rxrearm_start >=3D rxq->nb_rx_desc) > rxq->rxrearm_start =3D 0; The patch fixes the seg fault, but note I have only tested the default '#if= ndef RTE_LIBRTE_I40E_16BYTE_RX_DESC ' path Tested-by: David Coyle