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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN2PR11MB3550.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 93468cf7-6d55-4a22-e427-08d8e7d4c2a5 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Mar 2021 17:07:05.5731 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: uMNFL+Kgm//b+Nex12s3NA3wJbybvxOFtlvmNRrS/prEqMkUeloJyyxK3+Ijxwlt/IZy0kJPCJZYS8k1soUKhA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3934 X-OriginatorOrg: intel.com Subject: Re: [dpdk-stable] [dpdk-dev] [PATCH 1/3] net/iavf: fix segment fault in AVX512 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi Wenzhuo > -----Original Message----- > From: dev On Behalf Of Wenzhuo Lu > Sent: Friday, March 12, 2021 1:27 AM > To: dev@dpdk.org > Cc: Lu, Wenzhuo ; stable@dpdk.org > Subject: [dpdk-dev] [PATCH 1/3] net/iavf: fix segment fault in AVX512 >=20 > Fix segment fault when failing to get the memory from the pool. >=20 > Fixes: 31737f2b66fb ("net/iavf: enable AVX512 for legacy Rx") > Cc: stable@dpdk.org >=20 > Reported-by: David Coyle > Signed-off-by: Wenzhuo Lu > --- > drivers/net/iavf/iavf_rxtx_vec_avx512.c | 130 > ++++++++++++++++++++++++++++++++ > 1 file changed, 130 insertions(+) >=20 > diff --git a/drivers/net/iavf/iavf_rxtx_vec_avx512.c > b/drivers/net/iavf/iavf_rxtx_vec_avx512.c > index 5cb4c7c..6134520 100644 > --- a/drivers/net/iavf/iavf_rxtx_vec_avx512.c > +++ b/drivers/net/iavf/iavf_rxtx_vec_avx512.c > @@ -25,6 +25,9 @@ >=20 > rxdp =3D rxq->rx_ring + rxq->rxrearm_start; >=20 > + if (!cache) > + goto normal; [DC] In the Tx path, in iavf_tx_free_bufs_avx512(), it also checks for cach= e->len =3D=3D 0 Not sure if the extra check is necessary though - I don't know if 'cache' c= an be valid pointer but have a length of 0 if (!cache || cache->len =3D=3D 0) goto normal; > + > /* We need to pull 'n' more MBUFs into the software ring from > mempool > * We inline the mempool function here, so we can vectorize the > copy > * from the cache into the shadow ring. > @@ -127,6 +130,133 @@ > cache->len -=3D IAVF_DESCS_PER_LOOP_AVX; > } >=20 > + goto done; > + > +normal: > + /* Pull 'n' more MBUFs into the software ring */ > + if (rte_mempool_get_bulk(rxq->mp, > + (void *)rxp, > + IAVF_RXQ_REARM_THRESH) < 0) { > + if (rxq->rxrearm_nb + IAVF_RXQ_REARM_THRESH >=3D > + rxq->nb_rx_desc) { > + __m128i dma_addr0; > + > + dma_addr0 =3D _mm_setzero_si128(); > + for (i =3D 0; i < IAVF_DESCS_PER_LOOP_AVX; i++) { > + rxp[i] =3D &rxq->fake_mbuf; > + _mm_store_si128((__m128i *)&rxdp[i].read, > + dma_addr0); > + } > + } > + rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed > +=3D > + IAVF_RXQ_REARM_THRESH; > + return; > + } > + > +#ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC > + struct rte_mbuf *mb0, *mb1; > + __m128i dma_addr0, dma_addr1; > + __m128i hdr_room =3D _mm_set_epi64x(RTE_PKTMBUF_HEADROOM, > + RTE_PKTMBUF_HEADROOM); > + /* Initialize the mbufs in vector, process 4 mbufs in one loop */ [DC] Comment above should say 2 mbufs I think > + for (i =3D 0; i < IAVF_RXQ_REARM_THRESH; i +=3D 2, rxp +=3D 2) { > + __m128i vaddr0, vaddr1; > + > + mb0 =3D rxp[0]; > + mb1 =3D rxp[1]; > + > + /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */ > + RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=3D > + offsetof(struct rte_mbuf, buf_addr) + 8); > + vaddr0 =3D _mm_loadu_si128((__m128i *)&mb0->buf_addr); > + vaddr1 =3D _mm_loadu_si128((__m128i *)&mb1->buf_addr); > + > + /* convert pa to dma_addr hdr/data */ > + dma_addr0 =3D _mm_unpackhi_epi64(vaddr0, vaddr0); > + dma_addr1 =3D _mm_unpackhi_epi64(vaddr1, vaddr1); > + > + /* add headroom to pa values */ > + dma_addr0 =3D _mm_add_epi64(dma_addr0, hdr_room); > + dma_addr1 =3D _mm_add_epi64(dma_addr1, hdr_room); > + > + /* flush desc with pa dma_addr */ > + _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0); > + _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1); > + } [DC] Large blocks of the code above is the same as in avx2 file... any poss= ibility to have a common function or functions? > +#else > + struct rte_mbuf *mb0, *mb1, *mb2, *mb3; > + struct rte_mbuf *mb4, *mb5, *mb6, *mb7; > + __m512i dma_addr0_3, dma_addr4_7; > + __m512i hdr_room =3D > _mm512_set1_epi64(RTE_PKTMBUF_HEADROOM); > + /* Initialize the mbufs in vector, process 4 mbufs in one loop */ [DC] Comment above should say 8 mbufs > + for (i =3D 0; i < IAVF_RXQ_REARM_THRESH; > + i +=3D 8, rxp +=3D 8, rxdp +=3D 8) { > + > + /** > + * merge 0 & 1, by casting 0 to 256-bit and inserting 1 > + * into the high lanes. Similarly for 2 & 3 > + */ [DC] Comment above should say "Similarly for 2 & 3, 4 & 5, 6 & 7" > + vaddr0_1 =3D > + > _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr0), > + vaddr1, 1); > + vaddr2_3 =3D > + The patch fixes the seg fault, but note I have only tested the default '#ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC' path Tested-by: David Coyle