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From: Matan Azrad <matan@nvidia.com>
To: Tal Shnaiderman <talshn@nvidia.com>, "dev@dpdk.org" <dev@dpdk.org>
Cc: NBU-Contact-Thomas Monjalon <thomas@monjalon.net>,
	Shahaf Shuler <shahafs@nvidia.com>,
	Slava Ovsiienko <viacheslavo@nvidia.com>,
	"stable@dpdk.org" <stable@dpdk.org>
Subject: Re: [dpdk-stable] [PATCH v2] common/mlx5: split relaxed ordering set for read and write
Date: Tue, 3 Nov 2020 09:15:36 +0000	[thread overview]
Message-ID: <MW2PR12MB24922A2FA95E3857F53C45C1DF110@MW2PR12MB2492.namprd12.prod.outlook.com> (raw)
In-Reply-To: <20201103085122.8348-1-talshn@nvidia.com>



From: Tal Shnaiderman
> The current DevX implementation of the relaxed ordering feature is enabling
> relaxed ordering usage only if both relaxed ordering read AND write are
> supported.  In that case both relaxed ordering read and write are activated.
> 
> This commit will optimize the usage of relaxed ordering by enabling it when
> the read OR write features are supported.  Each relaxed ordering type will be
> activated according to its own capability bit.
> 
> This will align the DevX flow with the verbs implementation of ibv_reg_mr
> when using the flag IBV_ACCESS_RELAXED_ORDERING
> 
> Fixes: 53ac93f71ad1 ("net/mlx5: create relaxed ordering memory regions")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

  reply	other threads:[~2020-11-03  9:15 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-30 12:26 [dpdk-stable] [PATCH] " Tal Shnaiderman
2020-11-03  8:51 ` [dpdk-stable] [PATCH v2] " Tal Shnaiderman
2020-11-03  9:15   ` Matan Azrad [this message]
2020-11-04 18:04     ` Thomas Monjalon

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