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From: Matan Azrad <matan@nvidia.com>
To: Slava Ovsiienko <viacheslavo@nvidia.com>, "dev@dpdk.org" <dev@dpdk.org>
Cc: Raslan Darawsheh <rasland@nvidia.com>, Ori Kam <orika@nvidia.com>,
	NBU-Contact-Thomas Monjalon <thomas@monjalon.net>,
	"stable@dpdk.org" <stable@dpdk.org>
Subject: Re: [dpdk-stable] [PATCH 3/5] vdpa/mlx5: add timestamp format support
Date: Thu, 11 Mar 2021 19:55:10 +0000
Message-ID: <MW2PR12MB2492319E68A3633BDFA19941DF909@MW2PR12MB2492.namprd12.prod.outlook.com> (raw)
In-Reply-To: <20210307100251.22538-4-viacheslavo@nvidia.com>



From: Viacheslav Ovsiienko
> This patch adds support for the timestamp format settings for the queues pairs.
> If the firmware version x.30.256 or above is installed and the NIC timestamps
> are configured with the real-time format, the default zero values for new
> added values cause the queue creation reject. The patch queries the timestamp
> formats supported by the hardware and sets the configuration values in queue
> context accordingly.
> 
> Fixes: 95276abaaf0a ("vdpa/mlx5: introduce Mellanox vDPA driver")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
> ---
>  drivers/vdpa/mlx5/mlx5_vdpa.c       | 1 +
>  drivers/vdpa/mlx5/mlx5_vdpa.h       | 1 +
>  drivers/vdpa/mlx5/mlx5_vdpa_event.c | 8 ++++++++
>  3 files changed, 10 insertions(+)
> 
> diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.c b/drivers/vdpa/mlx5/mlx5_vdpa.c
> index 4c2d886bd7..af15977800 100644
> --- a/drivers/vdpa/mlx5/mlx5_vdpa.c
> +++ b/drivers/vdpa/mlx5/mlx5_vdpa.c
> @@ -745,6 +745,7 @@ mlx5_vdpa_pci_probe(struct rte_pci_driver *pci_drv
> __rte_unused,
>  	priv->caps = attr.vdpa;
>  	priv->log_max_rqt_size = attr.log_max_rqt_size;
>  	priv->num_lag_ports = attr.num_lag_ports;
> +	priv->qp_ts_format = attr.qp_ts_format;
>  	if (attr.num_lag_ports == 0)
>  		priv->num_lag_ports = 1;
>  	priv->ctx = ctx;
> diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h
> index 98c71aad4c..d93b430c97 100644
> --- a/drivers/vdpa/mlx5/mlx5_vdpa.h
> +++ b/drivers/vdpa/mlx5/mlx5_vdpa.h
> @@ -152,6 +152,7 @@ struct mlx5_vdpa_priv {
>  	struct mlx5_devx_obj *tiss[16]; /* TIS list for each LAG port. */
>  	uint16_t nr_virtqs;
>  	uint8_t num_lag_ports;
> +	uint8_t qp_ts_format;
>  	uint64_t features; /* Negotiated features. */
>  	uint16_t log_max_rqt_size;
>  	struct mlx5_vdpa_steer steer;
> diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_event.c
> b/drivers/vdpa/mlx5/mlx5_vdpa_event.c
> index 86adc864f5..fcc6b30a05 100644
> --- a/drivers/vdpa/mlx5/mlx5_vdpa_event.c
> +++ b/drivers/vdpa/mlx5/mlx5_vdpa_event.c
> @@ -662,6 +662,10 @@ mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv
> *priv, uint16_t desc_n,
>  	if (mlx5_vdpa_cq_create(priv, log_desc_n, callfd, &eqp->cq))
>  		return -1;
>  	attr.pd = priv->pdn;
> +	attr.ts_format =
> +		priv->qp_ts_format ==
> MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR ?
> +			MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING :
> +			MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;

Later on, we can think how we save this configuration in common for all the device drivers, with probably more other global managements...

>  	eqp->fw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
>  	if (!eqp->fw_qp) {
>  		DRV_LOG(ERR, "Failed to create FW QP(%u).", rte_errno); @@
> -692,6 +696,10 @@ mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv,
> uint16_t desc_n,
>  	attr.wq_umem_offset = 0;
>  	attr.dbr_umem_id = eqp->umem_obj->umem_id;
>  	attr.dbr_address = (1 << log_desc_n) * MLX5_WSEG_SIZE;
> +	attr.ts_format =
> +		priv->qp_ts_format ==
> MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR ?
> +			MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING :
> +			MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;
>  	eqp->sw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
>  	if (!eqp->sw_qp) {
>  		DRV_LOG(ERR, "Failed to create SW QP(%u).", rte_errno);
> --
> 2.28.0
Acked-by: Matan Azrad <matan@nvidia.com>

  reply	other threads:[~2021-03-11 19:55 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20210307100251.22538-1-viacheslavo@nvidia.com>
2021-03-07 10:02 ` [dpdk-stable] [PATCH 1/5] common/mlx5: add timestamp format support to DevX Viacheslav Ovsiienko
2021-03-11 19:36   ` Matan Azrad
2021-03-07 10:02 ` [dpdk-stable] [PATCH 2/5] net/mlx5: add timestamp format support Viacheslav Ovsiienko
2021-03-11 19:52   ` Matan Azrad
2021-03-07 10:02 ` [dpdk-stable] [PATCH 3/5] vdpa/mlx5: " Viacheslav Ovsiienko
2021-03-11 19:55   ` Matan Azrad [this message]
2021-03-07 10:02 ` [dpdk-stable] [PATCH 4/5] regex/mlx5: " Viacheslav Ovsiienko
2021-03-11 19:56   ` Matan Azrad
2021-03-07 10:02 ` [dpdk-stable] [PATCH 5/5] compress/mlx5: " Viacheslav Ovsiienko
2021-03-11 19:56   ` Matan Azrad
     [not found] ` <20210314115803.3110-1-viacheslavo@nvidia.com>
2021-03-14 11:57   ` [dpdk-stable] [PATCH 1/5] common/mlx5: add timestamp format support to DevX Viacheslav Ovsiienko
2021-03-14 11:58   ` [dpdk-stable] [PATCH 2/5] net/mlx5: add timestamp format support Viacheslav Ovsiienko
2021-03-14 11:58   ` [dpdk-stable] [PATCH 3/5] vdpa/mlx5: " Viacheslav Ovsiienko
2021-03-14 11:58   ` [dpdk-stable] [PATCH 4/5] regex/mlx5: " Viacheslav Ovsiienko
2021-03-14 11:58   ` [dpdk-stable] [PATCH 5/5] compress/mlx5: " Viacheslav Ovsiienko
     [not found] ` <20210314121302.5988-1-viacheslavo@nvidia.com>
2021-03-14 12:12   ` [dpdk-stable] [PATCH v3 1/5] common/mlx5: add timestamp format support to DevX Viacheslav Ovsiienko
2021-03-14 12:12   ` [dpdk-stable] [PATCH v3 2/5] net/mlx5: add timestamp format support Viacheslav Ovsiienko
2021-03-14 12:13   ` [dpdk-stable] [PATCH v3 3/5] vdpa/mlx5: " Viacheslav Ovsiienko
2021-03-14 12:13   ` [dpdk-stable] [PATCH v3 4/5] regex/mlx5: " Viacheslav Ovsiienko
2021-03-14 12:13   ` [dpdk-stable] [PATCH v3 5/5] compress/mlx5: " Viacheslav Ovsiienko

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