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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR11MB5013.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4b2fa281-33ac-41b0-b321-08dca573f9cd X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Jul 2024 08:47:51.0214 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: F+B0zQzU6ou/XFoQ9DZW3HpxwombgvqKu9Fylj1s0OcUKNWwvAlGgRSyEmNsYYnAfDYGLp4KqWGwLho2PHa6phr4/g3FMLTH7xVo+8Cg28o= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR11MB7907 X-OriginatorOrg: intel.com X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Acked-by: Arkadiusz Kusztal > -----Original Message----- > From: Dooley, Brian > Sent: Friday, July 12, 2024 4:49 PM > To: Ji, Kai > Cc: dev@dpdk.org; stable@dpdk.org; gakhil@marvell.com; Kusztal, Arkadiusz= X > ; Dooley, Brian > Subject: [PATCH v1] crypto/qat: add fix for Gen4 WRITE >=20 > All generations of QAT use the same Gen1 raw datapath. Gen4 needs a diffe= rent > WRITE function than other generations. Added separation for configuration= of > the raw ctx for Gen4 from the Gen1 codepath. >=20 > Fixes: 85fec6fd9674 ("crypto/qat: unify raw data path functions") > Cc: kai.ji@intel.com > Cc: stable@dpdk.org >=20 > Signed-off-by: Brian Dooley > --- > drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 121 ++++++++++++++++++- > drivers/crypto/qat/dev/qat_crypto_pmd_gens.h | 6 + > 2 files changed, 123 insertions(+), 4 deletions(-) >=20 > diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c > b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c > index 5e808a60bf..6a5d6e78b9 100644 > --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c > +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c > @@ -9,6 +9,7 @@ > #include "qat_asym.h" > #include "qat_crypto.h" > #include "qat_crypto_pmd_gens.h" > +#include "adf_transport_access_macros_gen4vf.h" >=20 >=20 > static struct rte_cryptodev_capabilities qat_sym_crypto_legacy_caps_gen4= [] =3D { > @@ -233,6 +234,78 @@ qat_sym_build_op_aead_gen4(void *in_op, struct > qat_sym_session *ctx, > return 0; > } >=20 > +int > +qat_sym_dp_enqueue_done_gen4(void *qp_data, uint8_t *drv_ctx, uint32_t > +n) { > + struct qat_qp *qp =3D qp_data; > + struct qat_queue *tx_queue =3D &qp->tx_q; > + struct qat_sym_dp_ctx *dp_ctx =3D (void *)drv_ctx; > + > + if (unlikely(dp_ctx->cached_enqueue !=3D n)) > + return -1; > + > + qp->enqueued +=3D n; > + qp->stats.enqueued_count +=3D n; > + > + tx_queue->tail =3D dp_ctx->tail; > + > + WRITE_CSR_RING_TAIL_GEN4VF(qp->mmap_bar_addr, > + tx_queue->hw_bundle_number, > + tx_queue->hw_queue_number, tx_queue->tail); > + > + tx_queue->csr_tail =3D tx_queue->tail; > + dp_ctx->cached_enqueue =3D 0; > + > + return 0; > +} > + > +int > +qat_sym_dp_dequeue_done_gen4(void *qp_data, uint8_t *drv_ctx, uint32_t > +n) { > + struct qat_qp *qp =3D qp_data; > + struct qat_queue *rx_queue =3D &qp->rx_q; > + struct qat_sym_dp_ctx *dp_ctx =3D (void *)drv_ctx; > + > + if (unlikely(dp_ctx->cached_dequeue !=3D n)) > + return -1; > + > + rx_queue->head =3D dp_ctx->head; > + rx_queue->nb_processed_responses +=3D n; > + qp->dequeued +=3D n; > + qp->stats.dequeued_count +=3D n; > + if (rx_queue->nb_processed_responses > > QAT_CSR_HEAD_WRITE_THRESH) { > + uint32_t old_head, new_head; > + uint32_t max_head; > + > + old_head =3D rx_queue->csr_head; > + new_head =3D rx_queue->head; > + max_head =3D qp->nb_descriptors * rx_queue->msg_size; > + > + /* write out free descriptors */ > + void *cur_desc =3D (uint8_t *)rx_queue->base_addr + old_head; > + > + if (new_head < old_head) { > + memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, > + max_head - old_head); > + memset(rx_queue->base_addr, > ADF_RING_EMPTY_SIG_BYTE, > + new_head); > + } else { > + memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, > new_head - > + old_head); > + } > + rx_queue->nb_processed_responses =3D 0; > + rx_queue->csr_head =3D new_head; > + > + /* write current head to CSR */ > + WRITE_CSR_RING_HEAD_GEN4VF(qp->mmap_bar_addr, > + rx_queue->hw_bundle_number, rx_queue- > >hw_queue_number, > + new_head); > + } > + > + dp_ctx->cached_dequeue =3D 0; > + return 0; > +} > + > int > qat_sym_crypto_set_session_gen4(void *cdev, void *session) { @@ -390,11 > +463,51 @@ qat_sym_configure_raw_dp_ctx_gen4(void *_raw_dp_ctx, void > *_ctx) { > struct rte_crypto_raw_dp_ctx *raw_dp_ctx =3D _raw_dp_ctx; > struct qat_sym_session *ctx =3D _ctx; > - int ret; >=20 > - ret =3D qat_sym_configure_raw_dp_ctx_gen1(_raw_dp_ctx, _ctx); > - if (ret < 0) > - return ret; > + raw_dp_ctx->enqueue_done =3D qat_sym_dp_enqueue_done_gen4; > + raw_dp_ctx->dequeue_burst =3D qat_sym_dp_dequeue_burst_gen1; > + raw_dp_ctx->dequeue =3D qat_sym_dp_dequeue_single_gen1; > + raw_dp_ctx->dequeue_done =3D qat_sym_dp_dequeue_done_gen4; > + > + if ((ctx->qat_cmd =3D=3D ICP_QAT_FW_LA_CMD_HASH_CIPHER || > + ctx->qat_cmd =3D=3D > ICP_QAT_FW_LA_CMD_CIPHER_HASH) && > + !ctx->is_gmac) { > + /* AES-GCM or AES-CCM */ > + if (ctx->qat_hash_alg =3D=3D > ICP_QAT_HW_AUTH_ALGO_GALOIS_128 || > + ctx->qat_hash_alg =3D=3D > ICP_QAT_HW_AUTH_ALGO_GALOIS_64 || > + (ctx->qat_cipher_alg =3D=3D > ICP_QAT_HW_CIPHER_ALGO_AES128 > + && ctx->qat_mode =3D=3D > ICP_QAT_HW_CIPHER_CTR_MODE > + && ctx->qat_hash_alg =3D=3D > + > ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC)) { > + raw_dp_ctx->enqueue_burst =3D > + > qat_sym_dp_enqueue_aead_jobs_gen1; > + raw_dp_ctx->enqueue =3D > + > qat_sym_dp_enqueue_single_aead_gen1; > + } else { > + raw_dp_ctx->enqueue_burst =3D > + > qat_sym_dp_enqueue_chain_jobs_gen1; > + raw_dp_ctx->enqueue =3D > + > qat_sym_dp_enqueue_single_chain_gen1; > + } > + } else if (ctx->qat_cmd =3D=3D ICP_QAT_FW_LA_CMD_AUTH || ctx- > >is_gmac) { > + raw_dp_ctx->enqueue_burst =3D > qat_sym_dp_enqueue_auth_jobs_gen1; > + raw_dp_ctx->enqueue =3D > qat_sym_dp_enqueue_single_auth_gen1; > + } else if (ctx->qat_cmd =3D=3D ICP_QAT_FW_LA_CMD_CIPHER) { > + if (ctx->qat_mode =3D=3D ICP_QAT_HW_CIPHER_AEAD_MODE || > + ctx->qat_cipher_alg =3D=3D > + > ICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305) { > + raw_dp_ctx->enqueue_burst =3D > + > qat_sym_dp_enqueue_aead_jobs_gen1; > + raw_dp_ctx->enqueue =3D > + > qat_sym_dp_enqueue_single_aead_gen1; > + } else { > + raw_dp_ctx->enqueue_burst =3D > + > qat_sym_dp_enqueue_cipher_jobs_gen1; > + raw_dp_ctx->enqueue =3D > + > qat_sym_dp_enqueue_single_cipher_gen1; > + } > + } else > + return -1; >=20 > if (ctx->is_single_pass && ctx->is_ucs) { > raw_dp_ctx->enqueue_burst =3D > qat_sym_dp_enqueue_aead_jobs_gen4; > diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h > b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h > index 1f5d2583c4..2c5816e696 100644 > --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h > +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h > @@ -1040,6 +1040,12 @@ qat_sym_dp_enqueue_done_gen1(void *qp_data, > uint8_t *drv_ctx, uint32_t n); int qat_sym_dp_dequeue_done_gen1(void > *qp_data, uint8_t *drv_ctx, uint32_t n); >=20 > +int > +qat_sym_dp_enqueue_done_gen4(void *qp_data, uint8_t *drv_ctx, uint32_t > +n); > + > +int > +qat_sym_dp_dequeue_done_gen4(void *qp_data, uint8_t *drv_ctx, uint32_t > +n); > + > int > qat_sym_configure_raw_dp_ctx_gen1(void *_raw_dp_ctx, void *_ctx); >=20 > -- > 2.25.1