From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 59163A0579 for ; Thu, 8 Apr 2021 09:54:46 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4FF9440138; Thu, 8 Apr 2021 09:54:46 +0200 (CEST) Received: from sender11-of-o51.zoho.eu (sender11-of-o51.zoho.eu [31.186.226.237]) by mails.dpdk.org (Postfix) with ESMTP id 3900240138; Thu, 8 Apr 2021 09:54:45 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; t=1617868483; cv=none; d=zohomail.eu; s=zohoarc; b=lpW3Og1jDWm2kJL9BjFbxiOSNeDF5ird020krCAiXqczFiSMXK7pn+mGddxeHs4tEY8PVRbBVbXTFXV5OFqtCDFVODNjujyjUeosD92R5+26Be/UF/gMXByV6QGjfcgFFw1s7lxUHQt+R+zQXOy/oUUv+wQXlfmhH91eFcIWmNM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.eu; s=zohoarc; t=1617868483; h=Content-Type:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=Nf25qgL1hCD/fNG3nstJokeIvabaFiKgdItJdNjM/lI=; b=g5/GwdNrqsv6iADMEkIj/2BeCE+o4IqT95rhPAhEuAAirH8Yvesp/HTMImnHgH2q3vI2zmaAyz9Nli70j1TohDcGFApqRnKItEDHcrn4lQ+PULigDLxiDCFUNXPiINC1KEfpLRiu57smFOGZ4wjXveFe39yP9qrsDAcGVeMARdQ= ARC-Authentication-Results: i=1; mx.zohomail.eu; spf=pass smtp.mailfrom=liangma@liangbit.com; dmarc=pass header.from= header.from= Received: from C02F33EJML85 (78.152.213.171 [78.152.213.171]) by mx.zoho.eu with SMTPS id 1617868482081261.7303762638054; Thu, 8 Apr 2021 09:54:42 +0200 (CEST) Date: Thu, 8 Apr 2021 08:54:39 +0100 From: Liang Ma To: Richael Zhuang Cc: "dev@dpdk.org" , "alan.carew@intel.com" , "stable@dpdk.org" , David Hunt , Pablo de Lara , nd Message-ID: References: <20210407023910.51052-1-richael.zhuang@arm.com> <20210407074636.26891-1-richael.zhuang@arm.com> <20210407074636.26891-4-richael.zhuang@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-ZohoMailClient: External Subject: Re: [dpdk-stable] [dpdk-dev] [PATCH v3 3/3] test/power: add delay before checking cpuinfo cur freq X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" On Thu, Apr 08, 2021 at 05:16:34AM +0000, Richael Zhuang wrote: > Hi Liang, > Sorry that last email contains "confidential notice", so I resend it. > > -----Original Message----- > > From: Liang Ma > > Sent: Wednesday, April 7, 2021 6:15 PM > > To: Richael Zhuang > > Cc: dev@dpdk.org; alan.carew@intel.com; stable@dpdk.org; David Hunt > > ; Pablo de Lara > > Subject: Re: [dpdk-dev] [PATCH v3 3/3] test/power: add delay before > > checking cpuinfo cur freq > > On Wed, Apr 07, 2021 at 03:46:36PM +0800, Richael Zhuang wrote: > > > Sleep for 1s before checking the newly updated value from > > > "/sys/devices/system/cpu/cpu%u/cpufreq/cpuinfo_cur_freq", because for > > > some systems it may not be effective immediately. > > > > > > Fixes: ed7c51a6a680 ("app/test: vm power management") > > > Cc: alan.carew@intel.com > > > Cc: stable@dpdk.org > > > > > > Signed-off-by: Richael Zhuang > > > --- > > > app/test/test_power_cpufreq.c | 3 +++ > > > 1 file changed, 3 insertions(+) > > > > > > diff --git a/app/test/test_power_cpufreq.c > > > b/app/test/test_power_cpufreq.c index cda74bd8a..7a93bc90a 100644 > > > --- a/app/test/test_power_cpufreq.c > > > +++ b/app/test/test_power_cpufreq.c > > > @@ -47,6 +47,9 @@ static uint32_t > > freqs[TEST_POWER_FREQS_NUM_MAX]; > > > static int check_cur_freq(unsigned lcore_id, uint32_t idx) { > > > +/* wait for the value to be updated */ > > > +sleep(1); > > Hi Richael, > > 1 second looks way too much for CPU frequency swap. > > The unit should be ms in the worst case regardless the vendor, IMO. > > Regards > > Liang > Thanks for review. Although I also think this time seems too long, > it needs more than 700ms when I tested on our arm platform. Hi Richael, I will suggest you talk with arm cpufreq driver maintainer(kernel). I don't think HW need 700ms to complete frequency changes. cpufreq driver might do something here. intel_pstate driver set the threshold as 10ms, according to the kernel source code. Regards Liang > > > + > > > #define TEST_POWER_CONVERT_TO_DECIMAL 10 > > > FILE *f; > > > char fullpath[PATH_MAX]; > > > -- > > > 2.20.1 > > > > IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.