From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 46C7FA0A0A for ; Sat, 8 May 2021 04:37:21 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3BEAB410F3; Sat, 8 May 2021 04:37:21 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 3554B4013F; Sat, 8 May 2021 04:37:17 +0200 (CEST) IronPort-SDR: J8AiNoim/NdZMShPdO8T282cv00MASXbFmLb5CY6EQoGJ2Hzh+pbXfUig1dXyGL2kwLr/SC2R+ PTehij6u/UEA== X-IronPort-AV: E=McAfee;i="6200,9189,9977"; a="260126754" X-IronPort-AV: E=Sophos;i="5.82,282,1613462400"; d="scan'208";a="260126754" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 May 2021 19:37:16 -0700 IronPort-SDR: roH1IHE9xKbAaq/N1xlDWylzZFSaTGm89P/AwLAsSbaVdbnoZgGCpvC/pJtxK5hMhq9VMo8JDn eiUasnlszBmg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,282,1613462400"; d="scan'208";a="466273210" Received: from irsmsx606.ger.corp.intel.com ([163.33.146.139]) by fmsmga002.fm.intel.com with ESMTP; 07 May 2021 19:37:15 -0700 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by IRSMSX606.ger.corp.intel.com (163.33.146.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Sat, 8 May 2021 03:37:13 +0100 Received: from shsmsx601.ccr.corp.intel.com ([10.109.6.141]) by SHSMSX601.ccr.corp.intel.com ([10.109.6.141]) with mapi id 15.01.2106.013; Sat, 8 May 2021 10:37:10 +0800 From: "Zhang, Qi Z" To: "Zhang, AlvinX" , "Yigit, Ferruh" CC: "dev@dpdk.org" , "stable@dpdk.org" Thread-Topic: [PATCH v2] net/ice: fix txq vector path selection Thread-Index: AQHXQ6hdyjk1K1q4VECg0ZabTEksG6rY18Sg Date: Sat, 8 May 2021 02:37:10 +0000 Message-ID: References: <20210425092639.1428-1-alvinx.zhang@intel.com> <20210508012032.14860-1-alvinx.zhang@intel.com> In-Reply-To: <20210508012032.14860-1-alvinx.zhang@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-stable] [PATCH v2] net/ice: fix txq vector path selection X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" > -----Original Message----- > From: Zhang, AlvinX > Sent: Saturday, May 8, 2021 9:21 AM > To: Zhang, Qi Z ; Yigit, Ferruh > Cc: dev@dpdk.org; Zhang, AlvinX ; stable@dpdk.org > Subject: [PATCH v2] net/ice: fix txq vector path selection >=20 > If Tx vector mode is disabled, the txq vector mode should be disabled too= . If vector mode is not allowed for Tx, no need to perform vector related set= up for Tx queue >=20 > This patch adds checking of Tx vector mode before enabling txq vector mod= e. The patch deferred vector setup for Tx queue to the place that vector mode = is confirmed to be allowed. >=20 > Fixes: 28f9002ab67f ("net/ice: add Tx AVX512 offload path") > Cc: stable@dpdk.org No need to add Cc stable, if you fix on current release.=20 >=20 > Signed-off-by: Alvin Zhang > --- >=20 > v2: Update commit log. > --- > drivers/net/ice/ice_rxtx.c | 16 +++++++++------- > 1 file changed, 9 insertions(+), 7 deletions(-) >=20 > diff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c inde= x > 92fbbc1..49abcb2 100644 > --- a/drivers/net/ice/ice_rxtx.c > +++ b/drivers/net/ice/ice_rxtx.c > @@ -3303,13 +3303,6 @@ > if (tx_check_ret >=3D 0 && > rte_vect_get_max_simd_bitwidth() >=3D RTE_VECT_SIMD_128) { > ad->tx_vec_allowed =3D true; > - for (i =3D 0; i < dev->data->nb_tx_queues; i++) { > - txq =3D dev->data->tx_queues[i]; > - if (txq && ice_txq_vec_setup(txq)) { > - ad->tx_vec_allowed =3D false; > - break; > - } > - } >=20 > if (rte_vect_get_max_simd_bitwidth() >=3D RTE_VECT_SIMD_512 > && > rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) =3D=3D 1 && > @@ -3329,6 +3322,15 @@ > if (!use_avx512 && tx_check_ret =3D=3D > ICE_VECTOR_OFFLOAD_PATH) > ad->tx_vec_allowed =3D false; >=20 > + if (ad->tx_vec_allowed) { > + for (i =3D 0; i < dev->data->nb_tx_queues; i++) { > + txq =3D dev->data->tx_queues[i]; > + if (txq && ice_txq_vec_setup(txq)) { > + ad->tx_vec_allowed =3D false; > + break; > + } > + } > + } > } else { > ad->tx_vec_allowed =3D false; > } > -- > 1.8.3.1