From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 390E3A04C8 for ; Fri, 18 Sep 2020 15:42:41 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BF4461D9C0; Fri, 18 Sep 2020 15:42:40 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 115171D8E9; Fri, 18 Sep 2020 15:42:36 +0200 (CEST) IronPort-SDR: zJ/BA2cWvoqUkF7jZzUQyJ4116y3XUWPqg0LCaCgkmxS7LRFeZVpt6FYzaf/R0NAGYMtMyAd3n IzgXTOn+gadg== X-IronPort-AV: E=McAfee;i="6000,8403,9747"; a="159237829" X-IronPort-AV: E=Sophos;i="5.77,274,1596524400"; d="scan'208";a="159237829" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2020 06:42:34 -0700 IronPort-SDR: ZovXj1zd/Q/gzmScf+C+mntHEdF5gbILdnD4EDyjQAp/DgnLqQQLrpfrZ45XojTFy29YFwyAFY WbYwZM/pzGGA== X-IronPort-AV: E=Sophos;i="5.77,274,1596524400"; d="scan'208";a="484214558" Received: from fyigit-mobl1.ger.corp.intel.com (HELO [10.213.227.248]) ([10.213.227.248]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2020 06:42:33 -0700 To: Igor Ryzhov , "Jiang, JunyuX" Cc: "dev@dpdk.org" , "Guo, Jia" , "Xing, Beilei" , "stable@dpdk.org" References: <20200910015426.3140-1-junyux.jiang@intel.com> <20200916015105.39815-1-junyux.jiang@intel.com> <295e61ad-cbc5-3fbe-c996-c3f9a11b34d6@intel.com> From: Ferruh Yigit Message-ID: Date: Fri, 18 Sep 2020 14:42:29 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.2.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Subject: Re: [dpdk-stable] [dpdk-dev] [PATCH v2] net/i40e: fix incorrect byte counters X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" On 9/18/2020 10:23 AM, Igor Ryzhov wrote: > Hi, > > Your code will work only if stats are updated at least once between two > overflows. > In this case it will have problems in 'i40e_stat_update_48()' too. It seems there is no way to detect if the increase in stats is N or MAX_48+N by the software. And obviously there is no way to detect if the overflow occurred more than once. > So it's still up to the application to handle this properly. I think it > should be mentioned in the docs. > +1 to document. > Igor > > On Fri, Sep 18, 2020 at 6:45 AM Jiang, JunyuX > wrote: > > Hi Ferruh, > > > -----Original Message----- > > From: Ferruh Yigit > > > Sent: Wednesday, September 16, 2020 8:31 PM > > To: Jiang, JunyuX >; dev@dpdk.org > > Cc: Guo, Jia >; > Xing, Beilei >; > > stable@dpdk.org > > Subject: Re: [dpdk-stable] [PATCH v2] net/i40e: fix incorrect > byte counters > > > > On 9/16/2020 2:51 AM, Junyu Jiang wrote: > > > This patch fixed the issue that rx/tx bytes overflowed > > > > "Rx/Tx statistics counters overflowed"? > > > Yes, the rx_bytes and tx_bytes counter in X710 cards is 48-bit long, > if keep sending packets for a log time, the register will overflow. > > > > on 48 bit limitation by enlarging the limitation. > > > > > > Fixes: 4861cde46116 ("i40e: new poll mode driver") > > > Cc: stable@dpdk.org > > > > > > Signed-off-by: Junyu Jiang > > > > --- > > >   drivers/net/i40e/i40e_ethdev.c | 47 > > ++++++++++++++++++++++++++++++++++ > > >   drivers/net/i40e/i40e_ethdev.h |  9 +++++++ > > >   2 files changed, 56 insertions(+) > > > > > > diff --git a/drivers/net/i40e/i40e_ethdev.c > > > b/drivers/net/i40e/i40e_ethdev.c index 563f21d9d..4d4ea9861 100644 > > > --- a/drivers/net/i40e/i40e_ethdev.c > > > +++ b/drivers/net/i40e/i40e_ethdev.c > > > @@ -3073,6 +3073,13 @@ i40e_update_vsi_stats(struct i40e_vsi *vsi) > > >     i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), > > I40E_GLV_BPRCL(idx), > > >                         vsi->offset_loaded, &oes->rx_broadcast, > > >                         &nes->rx_broadcast); > > > +   /* enlarge the limitation when rx_bytes overflowed */ > > > +   if (vsi->offset_loaded) { > > > +           if (I40E_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes- > > >rx_bytes) > > > +                   nes->rx_bytes += (uint64_t)1 << > I40E_48_BIT_WIDTH; > > > +           nes->rx_bytes += I40E_RXTX_BYTES_HIGH(vsi- > > >old_rx_bytes); > > > +   } > > > +   vsi->old_rx_bytes = nes->rx_bytes; > > > > > > Can you please describe this logic? (indeed better to describe it > in the > > commit log) > > > > 'nes->rx_bytes' is diff in the stats register since last read. > > 'old_rx_bytes' is the previous stats diff. > > > > Why/how "I40E_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes" has > > a meaning? Isn't this very depends on the read frequency? > > > > I guess I am missing something but please help me understand. > > > This patch fixes the issue of rx/tx bytes counter register overflow: > The counter register in i40e is 48-bit long, when overflow, > nes->rx_bytes becomes less than old_rx_bytes, the correct value of > nes->rx_bytes should be plused 1 << 48. > Use I40E_RXTX_BYTES_HIGH() to remember the MSB, nes->rx_bytes plus > the MSB is the correct value, So that using uint64_t to enlarge the > 48 bit  limitation of register . > > > Also can you please confirm the initial value of the > "vsi->offset_loaded" is > > correct. > > > offset_loaded will be true when get statistics of  port and > offset_loaded will be false when reset or clear the statistics, > so if  offset_loaded is false, shouldn't to calculate the value of > nes->rx_bytes, it will be 0. > > > <....> > > > > > @@ -282,6 +282,9 @@ struct rte_flow { > > >   #define I40E_ETH_OVERHEAD \ > > >     (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + > > I40E_VLAN_TAG_SIZE * 2) > > > > > > +#define I40E_RXTX_BYTES_HIGH(bytes) ((bytes) & ~I40E_48_BIT_MASK) > > > +#define I40E_RXTX_BYTES_LOW(bytes) ((bytes) & I40E_48_BIT_MASK) > > > + > > > > HIGH/LOW is a little misleading, for 64Bits it sounds like it is > getting low 32 bits > > and high 32 bits, can you please clarify macro masks out > > 48/16 bits. > > > Yes, I will change the macro name in V3. > > > > >   struct i40e_adapter; > > >   struct rte_pci_driver; > > > > > > @@ -399,6 +402,8 @@ struct i40e_vsi { > > >     uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing > enabled */ > > >     uint8_t vlan_filter_on; /* The VLAN filter enabled */ > > >     struct i40e_bw_info bw_info; /* VSI bandwidth information */ > > > +   uint64_t old_rx_bytes; > > > +   uint64_t old_tx_bytes; > > > > 'prev' seems better naming than 'old', what do you think renaming > > 'old_rx_bytes' -> 'prev_rx_bytes' (for all variables)? > Yes, it's better, I will fix it in V3. >