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From: checkpatch@dpdk.org
To: test-report@dpdk.org
Cc: <jerinj@marvell.com>
Subject: [dpdk-test-report] |WARNING| pw53974 [PATCH v2 03/27] common/octeontx2: add mbox request and response definition
Date: Sat,  1 Jun 2019 03:50:40 +0200 (CEST)	[thread overview]
Message-ID: <20190601015040.C57FE1B9C7@dpdk.org> (raw)
In-Reply-To: <20190601014905.45531-4-jerinj@marvell.com>

Test-Label: checkpatch
Test-Status: WARNING
http://dpdk.org/patch/53974

_coding style issues_


ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#150: FILE: drivers/common/octeontx2/otx2_mbox.h:105:
+#define MBOX_MESSAGES							\
+/* Generic mbox IDs (range 0x000 - 0x1FF) */				\
+M(READY,		0x001, ready, msg_req, ready_msg_rsp)		\
+M(ATTACH_RESOURCES,	0x002, attach_resources, rsrc_attach_req, msg_rsp)\
+M(DETACH_RESOURCES,	0x003, detach_resources, rsrc_detach_req, msg_rsp)\
+M(FREE_RSRC_CNT,	0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp)	\
+M(MSIX_OFFSET,		0x005, msix_offset, msg_req, msix_offset_rsp)	\
+M(VF_FLR,		0x006, vf_flr, msg_req, msg_rsp)		\
+M(PTP_OP,		0x007, ptp_op, ptp_req, ptp_rsp)		\
+M(GET_HW_CAP,		0x008, get_hw_cap, msg_req, get_hw_cap_rsp)	\
+M(NDC_SYNC_OP,		0x009, ndc_sync_op, ndc_sync_op, msg_rsp)	\
+/* CGX mbox IDs (range 0x200 - 0x3FF) */				\
+M(CGX_START_RXTX,	0x200, cgx_start_rxtx, msg_req, msg_rsp)	\
+M(CGX_STOP_RXTX,	0x201, cgx_stop_rxtx, msg_req, msg_rsp)		\
+M(CGX_STATS,		0x202, cgx_stats, msg_req, cgx_stats_rsp)	\
+M(CGX_MAC_ADDR_SET,	0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get,\
+				cgx_mac_addr_set_or_get)		\
+M(CGX_MAC_ADDR_GET,	0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get,\
+				cgx_mac_addr_set_or_get)		\
+M(CGX_PROMISC_ENABLE,	0x205, cgx_promisc_enable, msg_req, msg_rsp)	\
+M(CGX_PROMISC_DISABLE,	0x206, cgx_promisc_disable, msg_req, msg_rsp)	\
+M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp)	\
+M(CGX_STOP_LINKEVENTS,	0x208, cgx_stop_linkevents, msg_req, msg_rsp)	\
+M(CGX_GET_LINKINFO,	0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg)\
+M(CGX_INTLBK_ENABLE,	0x20A, cgx_intlbk_enable, msg_req, msg_rsp)	\
+M(CGX_INTLBK_DISABLE,	0x20B, cgx_intlbk_disable, msg_req, msg_rsp)	\
+M(CGX_PTP_RX_ENABLE,	0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp)	\
+M(CGX_PTP_RX_DISABLE,	0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp)	\
+M(CGX_CFG_PAUSE_FRM,	0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg,	\
+				cgx_pause_frm_cfg)			\
+M(CGX_FW_DATA_GET,	0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
+M(CGX_MAC_ADDR_ADD,     0x211, cgx_mac_addr_add, cgx_mac_addr_add_req,	\
+				cgx_mac_addr_add_rsp)			\
+M(CGX_MAC_ADDR_DEL,     0x212, cgx_mac_addr_del, cgx_mac_addr_del_req,	\
+				msg_rsp)				\
+M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req,	\
+				 cgx_max_dmac_entries_get_rsp)		\
+M(CGX_SET_LINK_STATE,	0x214, cgx_set_link_state,		\
+			cgx_set_link_state_msg, msg_rsp)		\
+/* NPA mbox IDs (range 0x400 - 0x5FF) */				\
+M(NPA_LF_ALLOC,		0x400, npa_lf_alloc, npa_lf_alloc_req,		\
+				npa_lf_alloc_rsp)			\
+M(NPA_LF_FREE,		0x401, npa_lf_free, msg_req, msg_rsp)		\
+M(NPA_AQ_ENQ,		0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp)\
+M(NPA_HWCTX_DISABLE,	0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
+/* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */				\
+M(SSO_LF_ALLOC,		0x600, sso_lf_alloc, sso_lf_alloc_req,		\
+				sso_lf_alloc_rsp)			\
+M(SSO_LF_FREE,		0x601, sso_lf_free, sso_lf_free_req, msg_rsp)	\
+M(SSOW_LF_ALLOC,	0x602, ssow_lf_alloc, ssow_lf_alloc_req, msg_rsp)\
+M(SSOW_LF_FREE,		0x603, ssow_lf_free, ssow_lf_free_req, msg_rsp)	\
+M(SSO_HW_SETCONFIG,	0x604, sso_hw_setconfig, sso_hw_setconfig,	\
+				msg_rsp)				\
+M(SSO_GRP_SET_PRIORITY,	0x605, sso_grp_set_priority, sso_grp_priority,	\
+				msg_rsp)				\
+M(SSO_GRP_GET_PRIORITY,	0x606, sso_grp_get_priority, sso_info_req,	\
+				sso_grp_priority)			\
+M(SSO_WS_CACHE_INV,	0x607, sso_ws_cache_inv, msg_req, msg_rsp)	\
+M(SSO_GRP_QOS_CONFIG,	0x608, sso_grp_qos_config, sso_grp_qos_cfg,	\
+				msg_rsp)				\
+M(SSO_GRP_GET_STATS,	0x609, sso_grp_get_stats, sso_info_req,		\
+				sso_grp_stats)				\
+M(SSO_HWS_GET_STATS,	0x610, sso_hws_get_stats, sso_info_req,		\
+				sso_hws_stats)				\
+/* TIM mbox IDs (range 0x800 - 0x9FF) */				\
+M(TIM_LF_ALLOC,		0x800, tim_lf_alloc, tim_lf_alloc_req,		\
+				tim_lf_alloc_rsp)			\
+M(TIM_LF_FREE,		0x801, tim_lf_free, tim_ring_req, msg_rsp)	\
+M(TIM_CONFIG_RING,	0x802, tim_config_ring, tim_config_req, msg_rsp)\
+M(TIM_ENABLE_RING,	0x803, tim_enable_ring, tim_ring_req,		\
+				tim_enable_rsp)				\
+M(TIM_DISABLE_RING,	0x804, tim_disable_ring, tim_ring_req, msg_rsp)	\
+/* CPT mbox IDs (range 0xA00 - 0xBFF) */				\
+M(CPT_RD_WR_REGISTER,	0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg,	\
+			       cpt_rd_wr_reg_msg)			\
+M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg,			\
+			       cpt_inline_ipsec_cfg_msg, msg_rsp)	\
+/* NPC mbox IDs (range 0x6000 - 0x7FFF) */				\
+M(NPC_MCAM_ALLOC_ENTRY,	0x6000, npc_mcam_alloc_entry,			\
+				npc_mcam_alloc_entry_req,		\
+				npc_mcam_alloc_entry_rsp)		\
+M(NPC_MCAM_FREE_ENTRY,	0x6001, npc_mcam_free_entry,			\
+				npc_mcam_free_entry_req, msg_rsp)	\
+M(NPC_MCAM_WRITE_ENTRY,	0x6002, npc_mcam_write_entry,			\
+				npc_mcam_write_entry_req, msg_rsp)	\
+M(NPC_MCAM_ENA_ENTRY,	0x6003, npc_mcam_ena_entry,			\
+				npc_mcam_ena_dis_entry_req, msg_rsp)	\
+M(NPC_MCAM_DIS_ENTRY,	0x6004, npc_mcam_dis_entry,			\
+				npc_mcam_ena_dis_entry_req, msg_rsp)	\
+M(NPC_MCAM_SHIFT_ENTRY,	0x6005, npc_mcam_shift_entry,			\
+				npc_mcam_shift_entry_req,		\
+				npc_mcam_shift_entry_rsp)		\
+M(NPC_MCAM_ALLOC_COUNTER,	0x6006, npc_mcam_alloc_counter,		\
+				npc_mcam_alloc_counter_req,		\
+				npc_mcam_alloc_counter_rsp)		\
+M(NPC_MCAM_FREE_COUNTER,	0x6007, npc_mcam_free_counter,		\
+				npc_mcam_oper_counter_req,		\
+				msg_rsp)				\
+M(NPC_MCAM_UNMAP_COUNTER,	0x6008, npc_mcam_unmap_counter,		\
+				npc_mcam_unmap_counter_req,		\
+				msg_rsp)				\
+M(NPC_MCAM_CLEAR_COUNTER,	0x6009, npc_mcam_clear_counter,		\
+				npc_mcam_oper_counter_req,		\
+				msg_rsp)				\
+M(NPC_MCAM_COUNTER_STATS,	0x600a, npc_mcam_counter_stats,		\
+				npc_mcam_oper_counter_req,		\
+				npc_mcam_oper_counter_rsp)		\
+M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry,\
+				npc_mcam_alloc_and_write_entry_req,	\
+				npc_mcam_alloc_and_write_entry_rsp)	\
+M(NPC_GET_KEX_CFG,	  0x600c, npc_get_kex_cfg, msg_req,		\
+				npc_get_kex_cfg_rsp)			\
+/* NIX mbox IDs (range 0x8000 - 0xFFFF) */				\
+M(NIX_LF_ALLOC,		0x8000, nix_lf_alloc, nix_lf_alloc_req,		\
+				nix_lf_alloc_rsp)			\
+M(NIX_LF_FREE,		0x8001, nix_lf_free, nix_lf_free_req, msg_rsp)	\
+M(NIX_AQ_ENQ,		0x8002, nix_aq_enq, nix_aq_enq_req,		\
+				nix_aq_enq_rsp)				\
+M(NIX_HWCTX_DISABLE,	0x8003, nix_hwctx_disable, hwctx_disable_req,	\
+				msg_rsp)				\
+M(NIX_TXSCH_ALLOC,	0x8004, nix_txsch_alloc, nix_txsch_alloc_req,	\
+				nix_txsch_alloc_rsp)			\
+M(NIX_TXSCH_FREE,	0x8005, nix_txsch_free,	nix_txsch_free_req,	\
+				msg_rsp)				\
+M(NIX_TXSCHQ_CFG,	0x8006, nix_txschq_cfg, nix_txschq_config,	\
+				msg_rsp)				\
+M(NIX_STATS_RST,	0x8007, nix_stats_rst, msg_req, msg_rsp)	\
+M(NIX_VTAG_CFG,		0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp)	\
+M(NIX_RSS_FLOWKEY_CFG,	0x8009, nix_rss_flowkey_cfg,			\
+				nix_rss_flowkey_cfg,			\
+				nix_rss_flowkey_cfg_rsp)		\
+M(NIX_SET_MAC_ADDR,	0x800a, nix_set_mac_addr, nix_set_mac_addr,	\
+				msg_rsp)				\
+M(NIX_SET_RX_MODE,	0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp)	\
+M(NIX_SET_HW_FRS,	0x800c, nix_set_hw_frs,	nix_frs_cfg, msg_rsp)	\
+M(NIX_LF_START_RX,	0x800d, nix_lf_start_rx, msg_req, msg_rsp)	\
+M(NIX_LF_STOP_RX,	0x800e, nix_lf_stop_rx,	msg_req, msg_rsp)	\
+M(NIX_MARK_FORMAT_CFG,	0x800f, nix_mark_format_cfg,			\
+				nix_mark_format_cfg,			\
+				nix_mark_format_cfg_rsp)		\
+M(NIX_LSO_FORMAT_CFG,	0x8011, nix_lso_format_cfg, nix_lso_format_cfg,	\
+				nix_lso_format_cfg_rsp)			\
+M(NIX_LF_PTP_TX_ENABLE,	0x8013, nix_lf_ptp_tx_enable, msg_req,		\
+				msg_rsp)				\
+M(NIX_LF_PTP_TX_DISABLE,	0x8014, nix_lf_ptp_tx_disable, msg_req,	\
+				msg_rsp)				\
+M(NIX_SET_VLAN_TPID,	0x8015, nix_set_vlan_tpid, nix_set_vlan_tpid,	\
+				msg_rsp)				\
+M(NIX_BP_ENABLE,	0x8016, nix_bp_enable, nix_bp_cfg_req,		\
+				nix_bp_cfg_rsp)				\
+M(NIX_BP_DISABLE,	0x8017, nix_bp_disable,	nix_bp_cfg_req, msg_rsp)\
+M(NIX_GET_MAC_ADDR,	0x8018, nix_get_mac_addr, msg_req,		\
+				nix_get_mac_addr_rsp)			\
+M(NIX_INLINE_IPSEC_CFG,	0x8019, nix_inline_ipsec_cfg,			\
+				nix_inline_ipsec_cfg, msg_rsp)		\
+M(NIX_INLINE_IPSEC_LF_CFG,						\
+			0x801a, nix_inline_ipsec_lf_cfg,		\
+				nix_inline_ipsec_lf_cfg, msg_rsp)

ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#310: FILE: drivers/common/octeontx2/otx2_mbox.h:265:
+#define MBOX_UP_CGX_MESSAGES						\
+M(CGX_LINK_EVENT,	0xC00, cgx_link_event, cgx_link_info_msg,	\
+				msg_rsp)				\
+M(CGX_PTP_RX_INFO,	0xC01, cgx_ptp_rx_info, cgx_ptp_rx_info_msg,	\
+				msg_rsp)

ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#317: FILE: drivers/common/octeontx2/otx2_mbox.h:272:
+#define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,

total: 3 errors, 0 warnings, 1332 lines checked

           reply	other threads:[~2019-06-01  1:50 UTC|newest]

Thread overview: expand[flat|nested]  mbox.gz  Atom feed
 [parent not found: <20190601014905.45531-4-jerinj@marvell.com>]

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