Test-Label: iol-testing Test-Status: WARNING http://dpdk.org/patch/103811 _apply patch failure_ Submitter: Kai Ji Date: Friday, November 05 2021 00:19:32 Applied on: CommitID:65d9b7c664cc8cc090ced1c3260d803f306a2bba Apply patch set 103811-103821 failed: Checking patch drivers/common/qat/qat_qp.c... Hunk #1 succeeded at 715 (offset 165 lines). Hunk #2 succeeded at 984 (offset 165 lines). Checking patch drivers/common/qat/qat_qp.h... Hunk #1 succeeded at 78 (offset 42 lines). Hunk #2 succeeded at 131 (offset 42 lines). error: while searching for: }; uint16_t qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops); uint16_t qat_enqueue_comp_op_burst(void *qp, void **ops, uint16_t nb_ops); uint16_t qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops); int qat_qp_release(enum qat_device_gen qat_dev_gen, struct qat_qp **qp_addr); error: patch failed: drivers/common/qat/qat_qp.h:78 Checking patch drivers/compress/qat/qat_comp_pmd.c... Hunk #1 succeeded at 637 (offset 17 lines). Checking patch drivers/crypto/qat/qat_asym_pmd.c... Hunk #1 succeeded at 212 (offset 150 lines). Checking patch drivers/crypto/qat/qat_sym_pmd.c... Hunk #1 succeeded at 317 (offset 268 lines). Checking patch drivers/crypto/qat/qat_sym_session.h... Applied patch drivers/common/qat/qat_qp.c cleanly. Applying patch drivers/common/qat/qat_qp.h with 1 reject... Hunk #1 applied cleanly. Hunk #2 applied cleanly. Rejected hunk #3. Applied patch drivers/compress/qat/qat_comp_pmd.c cleanly. Applied patch drivers/crypto/qat/qat_asym_pmd.c cleanly. Applied patch drivers/crypto/qat/qat_sym_pmd.c cleanly. Applied patch drivers/crypto/qat/qat_sym_session.h cleanly. diff a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h (rejected hunks) @@ -78,13 +124,15 @@ struct qat_qp_config { }; uint16_t -qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops); +qat_enqueue_op_burst(void *qp, qat_op_build_request_t op_build_request, + void **ops, uint16_t nb_ops); uint16_t qat_enqueue_comp_op_burst(void *qp, void **ops, uint16_t nb_ops); uint16_t -qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops); +qat_dequeue_op_burst(void *qp, void **ops, + qat_op_dequeue_t qat_dequeue_process_response, uint16_t nb_ops); int qat_qp_release(enum qat_device_gen qat_dev_gen, struct qat_qp **qp_addr); Checking patch drivers/crypto/qat/dev/qat_crypto_pmd_gens.h... error: drivers/crypto/qat/dev/qat_crypto_pmd_gens.h: does not exist in index Checking patch drivers/crypto/qat/dev/qat_sym_pmd_gen1.c... error: drivers/crypto/qat/dev/qat_sym_pmd_gen1.c: does not exist in index Checking patch drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c... error: drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c: does not exist in index Checking patch drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c... error: drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c: does not exist in index Checking patch drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c... error: drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c: does not exist in index Checking patch drivers/crypto/qat/dev/qat_sym_pmd_gen1.c... error: drivers/crypto/qat/dev/qat_sym_pmd_gen1.c: does not exist in index Checking patch drivers/crypto/qat/qat_crypto.c... error: drivers/crypto/qat/qat_crypto.c: does not exist in index Checking patch drivers/crypto/qat/qat_crypto.h... error: drivers/crypto/qat/qat_crypto.h: does not exist in index Checking patch drivers/crypto/qat/qat_sym.c... Checking patch drivers/crypto/qat/qat_sym_session.c... error: while searching for: return 0; } static void qat_sym_session_set_ext_hash_flags(struct qat_sym_session *session, uint8_t hash_flag) { struct icp_qat_fw_comn_req_hdr *header = &session->fw_req.comn_hdr; struct icp_qat_fw_cipher_auth_cd_ctrl_hdr *cd_ctrl = (struct icp_qat_fw_cipher_auth_cd_ctrl_hdr *) session->fw_req.cd_ctrl.content_desc_ctrl_lw; /* Set the Use Extended Protocol Flags bit in LW 1 */ QAT_FIELD_SET(header->comn_req_flags, QAT_COMN_EXT_FLAGS_USED, QAT_COMN_EXT_FLAGS_BITPOS, QAT_COMN_EXT_FLAGS_MASK); /* Set Hash Flags in LW 28 */ cd_ctrl->hash_flags |= hash_flag; /* Set proto flags in LW 1 */ switch (session->qat_cipher_alg) { case ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2: ICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags, ICP_QAT_FW_LA_SNOW_3G_PROTO); ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET( header->serv_specif_flags, 0); break; case ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3: ICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags, ICP_QAT_FW_LA_NO_PROTO); ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET( header->serv_specif_flags, ICP_QAT_FW_LA_ZUC_3G_PROTO); break; default: ICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags, ICP_QAT_FW_LA_NO_PROTO); ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET( header->serv_specif_flags, 0); break; } } static void qat_sym_session_handle_mixed(const struct rte_cryptodev *dev, struct qat_sym_session *session) { const struct qat_cryptodev_private *qat_private = dev->data->dev_private; enum qat_device_gen min_dev_gen = (qat_private->internal_capabilities & QAT_SYM_CAP_MIXED_CRYPTO) ? QAT_GEN2 : QAT_GEN3; if (session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 && session->qat_cipher_alg != ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) { session->min_qat_dev_gen = min_dev_gen; qat_sym_session_set_ext_hash_flags(session, 1 << ICP_QAT_FW_AUTH_HDR_FLAG_ZUC_EIA3_BITPOS); } else if (session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 && session->qat_cipher_alg != ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) { session->min_qat_dev_gen = min_dev_gen; qat_sym_session_set_ext_hash_flags(session, 1 << ICP_QAT_FW_AUTH_HDR_FLAG_SNOW3G_UIA2_BITPOS); } else if ((session->aes_cmac || session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) && (session->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 || session->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3)) { session->min_qat_dev_gen = min_dev_gen; qat_sym_session_set_ext_hash_flags(session, 0); } } int qat_sym_session_set_parameters(struct rte_cryptodev *dev, struct rte_crypto_sym_xform *xform, void *session_private) error: patch failed: drivers/crypto/qat/qat_sym_session.c:486 Hunk #2 succeeded at 568 (offset 73 lines). Hunk #3 succeeded at 582 (offset 73 lines). Hunk #4 succeeded at 623 (offset 73 lines). Hunk #5 succeeded at 640 (offset 73 lines). Hunk #6 succeeded at 660 (offset 73 lines). Hunk #7 succeeded at 671 (offset 73 lines). Hunk #8 succeeded at 1197 (offset 73 lines). Hunk #9 succeeded at 1647 (offset 73 lines). Hunk #10 succeeded at 1994 (offset 73 lines). Hunk #11 succeeded at 2254 (offset 73 lines). Hunk #12 succeeded at 2278 (offset 73 lines). Hunk #13 succeeded at 2304 (offset 73 lines). Checking patch drivers/crypto/qat/qat_sym_session.h... error: drivers/crypto/qat/qat_sym_session.h: does not match index Applied patch drivers/crypto/qat/qat_sym.c cleanly. Applying patch drivers/crypto/qat/qat_sym_session.c with 1 reject... Rejected hunk #1. Hunk #2 applied cleanly. Hunk #3 applied cleanly. Hunk #4 applied cleanly. Hunk #5 applied cleanly. Hunk #6 applied cleanly. Hunk #7 applied cleanly. Hunk #8 applied cleanly. Hunk #9 applied cleanly. Hunk #10 applied cleanly. Hunk #11 applied cleanly. Hunk #12 applied cleanly. Hunk #13 applied cleanly. diff a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c (rejected hunks) @@ -486,80 +486,6 @@ qat_sym_session_configure(struct rte_cryptodev *dev, return 0; } -static void -qat_sym_session_set_ext_hash_flags(struct qat_sym_session *session, - uint8_t hash_flag) -{ - struct icp_qat_fw_comn_req_hdr *header = &session->fw_req.comn_hdr; - struct icp_qat_fw_cipher_auth_cd_ctrl_hdr *cd_ctrl = - (struct icp_qat_fw_cipher_auth_cd_ctrl_hdr *) - session->fw_req.cd_ctrl.content_desc_ctrl_lw; - - /* Set the Use Extended Protocol Flags bit in LW 1 */ - QAT_FIELD_SET(header->comn_req_flags, - QAT_COMN_EXT_FLAGS_USED, - QAT_COMN_EXT_FLAGS_BITPOS, - QAT_COMN_EXT_FLAGS_MASK); - - /* Set Hash Flags in LW 28 */ - cd_ctrl->hash_flags |= hash_flag; - - /* Set proto flags in LW 1 */ - switch (session->qat_cipher_alg) { - case ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2: - ICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags, - ICP_QAT_FW_LA_SNOW_3G_PROTO); - ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET( - header->serv_specif_flags, 0); - break; - case ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3: - ICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags, - ICP_QAT_FW_LA_NO_PROTO); - ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET( - header->serv_specif_flags, - ICP_QAT_FW_LA_ZUC_3G_PROTO); - break; - default: - ICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags, - ICP_QAT_FW_LA_NO_PROTO); - ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET( - header->serv_specif_flags, 0); - break; - } -} - -static void -qat_sym_session_handle_mixed(const struct rte_cryptodev *dev, - struct qat_sym_session *session) -{ - const struct qat_cryptodev_private *qat_private = - dev->data->dev_private; - enum qat_device_gen min_dev_gen = (qat_private->internal_capabilities & - QAT_SYM_CAP_MIXED_CRYPTO) ? QAT_GEN2 : QAT_GEN3; - - if (session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 && - session->qat_cipher_alg != - ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) { - session->min_qat_dev_gen = min_dev_gen; - qat_sym_session_set_ext_hash_flags(session, - 1 << ICP_QAT_FW_AUTH_HDR_FLAG_ZUC_EIA3_BITPOS); - } else if (session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 && - session->qat_cipher_alg != - ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) { - session->min_qat_dev_gen = min_dev_gen; - qat_sym_session_set_ext_hash_flags(session, - 1 << ICP_QAT_FW_AUTH_HDR_FLAG_SNOW3G_UIA2_BITPOS); - } else if ((session->aes_cmac || - session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) && - (session->qat_cipher_alg == - ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 || - session->qat_cipher_alg == - ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3)) { - session->min_qat_dev_gen = min_dev_gen; - qat_sym_session_set_ext_hash_flags(session, 0); - } -} - int qat_sym_session_set_parameters(struct rte_cryptodev *dev, struct rte_crypto_sym_xform *xform, void *session_private) Checking patch drivers/common/qat/qat_qp.c... error: drivers/common/qat/qat_qp.c: does not match index Checking patch drivers/crypto/qat/dev/qat_asym_pmd_gen1.c... error: drivers/crypto/qat/dev/qat_asym_pmd_gen1.c: does not exist in index Checking patch drivers/crypto/qat/dev/qat_crypto_pmd_gens.h... error: drivers/crypto/qat/dev/qat_crypto_pmd_gens.h: does not exist in index Checking patch drivers/crypto/qat/qat_asym.c... error: while searching for: /* SPDX-License-Identifier: BSD-3-Clause * Copyright(c) 2019 Intel Corporation */ #include #include "qat_asym.h" #include "icp_qat_fw_pke.h" #include "icp_qat_fw.h" #include "qat_pke_functionality_arrays.h" #define qat_asym_sz_2param(arg) (arg, sizeof(arg)/sizeof(*arg)) static int qat_asym_get_sz_and_func_id(const uint32_t arr[][2], size_t arr_sz, size_t *size, uint32_t *func_id) { size_t i; for (i = 0; i < arr_sz; i++) { if (*size <= arr[i][0]) { *size = arr[i][0]; *func_id = arr[i][1]; return 0; } } return -1; } static inline void qat_fill_req_tmpl(struct icp_qat_fw_pke_request *qat_req) { memset(qat_req, 0, sizeof(*qat_req)); qat_req->pke_hdr.service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_PKE; qat_req->pke_hdr.hdr_flags = ICP_QAT_FW_COMN_HDR_FLAGS_BUILD (ICP_QAT_FW_COMN_REQ_FLAG_SET); } static inline void qat_asym_build_req_tmpl(void *sess_private_data) { struct icp_qat_fw_pke_request *qat_req; struct qat_asym_session *session = sess_private_data; qat_req = &session->req_tmpl; qat_fill_req_tmpl(qat_req); } static size_t max_of(int n, ...) { va_list args; size_t len = 0, num; int i; va_start(args, n); len = va_arg(args, size_t); for (i = 0; i < n - 1; i++) { num = va_arg(args, size_t); if (num > len) len = num; } va_end(args); return len; } static void qat_clear_arrays(struct qat_asym_op_cookie *cookie, int in_count, int out_count, int alg_size) { error: patch failed: drivers/crypto/qat/qat_asym.c:1 error: while searching for: } } static int qat_asym_check_nonzero(rte_crypto_param n) { if (n.length < 8) { /* Not a case for any cryptograpic function except for DH error: patch failed: drivers/crypto/qat/qat_asym.c:106 Hunk #3 succeeded at 457 (offset -287 lines). error: while searching for: return 0; } static void qat_asym_collect_response(struct rte_crypto_op *rx_op, struct qat_asym_op_cookie *cookie, struct rte_crypto_asym_xform *xform) { size_t alg_size, alg_size_in_bytes = 0; struct rte_crypto_asym_op *asym_op = rx_op->asym; if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODEX) { rte_crypto_param n = xform->modex.modulus; alg_size = cookie->alg_size; alg_size_in_bytes = alg_size >> 3; uint8_t *modexp_result = asym_op->modex.result.data; if (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED) { rte_memcpy(modexp_result + (asym_op->modex.result.length - n.length), cookie->output_array[0] + alg_size_in_bytes - n.length, n.length ); rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS; #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG QAT_DP_HEXDUMP_LOG(DEBUG, "ModExp result", cookie->output_array[0], alg_size_in_bytes); #endif } } else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODINV) { rte_crypto_param n = xform->modinv.modulus; alg_size = cookie->alg_size; alg_size_in_bytes = alg_size >> 3; uint8_t *modinv_result = asym_op->modinv.result.data; if (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED) { rte_memcpy(modinv_result + (asym_op->modinv.result.length - n.length), cookie->output_array[0] + alg_size_in_bytes - n.length, n.length); rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS; #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG QAT_DP_HEXDUMP_LOG(DEBUG, "ModInv result", cookie->output_array[0], alg_size_in_bytes); #endif } } else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_RSA) { alg_size = cookie->alg_size; alg_size_in_bytes = alg_size >> 3; if (asym_op->rsa.op_type == RTE_CRYPTO_ASYM_OP_ENCRYPT || asym_op->rsa.op_type == RTE_CRYPTO_ASYM_OP_VERIFY) { if (asym_op->rsa.op_type == RTE_CRYPTO_ASYM_OP_ENCRYPT) { uint8_t *rsa_result = asym_op->rsa.cipher.data; rte_memcpy(rsa_result, cookie->output_array[0], alg_size_in_bytes); rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS; #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG QAT_DP_HEXDUMP_LOG(DEBUG, "RSA Encrypted data", cookie->output_array[0], alg_size_in_bytes); #endif } else if (asym_op->rsa.op_type == RTE_CRYPTO_ASYM_OP_VERIFY) { uint8_t *rsa_result = asym_op->rsa.cipher.data; switch (asym_op->rsa.pad) { case RTE_CRYPTO_RSA_PADDING_NONE: rte_memcpy(rsa_result, cookie->output_array[0], alg_size_in_bytes); rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS; #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG QAT_DP_HEXDUMP_LOG(DEBUG, "RSA Signature", cookie->output_array[0], alg_size_in_bytes); #endif break; default: QAT_LOG(ERR, "Padding not supported"); rx_op->status = RTE_CRYPTO_OP_STATUS_ERROR; break; } } } else { if (asym_op->rsa.op_type == RTE_CRYPTO_ASYM_OP_DECRYPT) { uint8_t *rsa_result = asym_op->rsa.message.data; switch (asym_op->rsa.pad) { case RTE_CRYPTO_RSA_PADDING_NONE: rte_memcpy(rsa_result, cookie->output_array[0], alg_size_in_bytes); rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS; break; default: QAT_LOG(ERR, "Padding not supported"); rx_op->status = RTE_CRYPTO_OP_STATUS_ERROR; break; } #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG QAT_DP_HEXDUMP_LOG(DEBUG, "RSA Decrypted Message", rsa_result, alg_size_in_bytes); #endif } else if (asym_op->rsa.op_type == RTE_CRYPTO_ASYM_OP_SIGN) { uint8_t *rsa_result = asym_op->rsa.sign.data; rte_memcpy(rsa_result, cookie->output_array[0], alg_size_in_bytes); rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS; #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG QAT_DP_HEXDUMP_LOG(DEBUG, "RSA Signature", cookie->output_array[0], alg_size_in_bytes); #endif } } } qat_clear_arrays_by_alg(cookie, xform, alg_size_in_bytes); } void qat_asym_process_response(void **op, uint8_t *resp, void *op_cookie) { struct qat_asym_session *ctx; struct icp_qat_fw_pk error: patch failed: drivers/crypto/qat/qat_asym.c:545 Checking patch drivers/crypto/qat/qat_asym.h... Applying patch drivers/crypto/qat/qat_asym.c with 3 rejects... Rejected hunk #1. Rejected hunk #2. Hunk #3 applied cleanly. Rejected hunk #4. Applied patch drivers/crypto/qat/qat_asym.h cleanly. diff a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c (rejected hunks) @@ -1,69 +1,115 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2019 Intel Corporation + * Copyright(c) 2019 - 2021 Intel Corporation */ #include -#include "qat_asym.h" +#include + #include "icp_qat_fw_pke.h" #include "icp_qat_fw.h" #include "qat_pke_functionality_arrays.h" -#define qat_asym_sz_2param(arg) (arg, sizeof(arg)/sizeof(*arg)) +#include "qat_device.h" -static int qat_asym_get_sz_and_func_id(const uint32_t arr[][2], - size_t arr_sz, size_t *size, uint32_t *func_id) +#include "qat_logs.h" +#include "qat_asym.h" + +int +qat_asym_session_configure(struct rte_cryptodev *dev, + struct rte_crypto_asym_xform *xform, + struct rte_cryptodev_asym_session *sess, + struct rte_mempool *mempool) { - size_t i; + int err = 0; + void *sess_private_data; + struct qat_asym_session *session; - for (i = 0; i < arr_sz; i++) { - if (*size <= arr[i][0]) { - *size = arr[i][0]; - *func_id = arr[i][1]; - return 0; + if (rte_mempool_get(mempool, &sess_private_data)) { + QAT_LOG(ERR, + "Couldn't get object from session mempool"); + return -ENOMEM; + } + + session = sess_private_data; + if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODEX) { + if (xform->modex.exponent.length == 0 || + xform->modex.modulus.length == 0) { + QAT_LOG(ERR, "Invalid mod exp input parameter"); + err = -EINVAL; + goto error; + } + } else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODINV) { + if (xform->modinv.modulus.length == 0) { + QAT_LOG(ERR, "Invalid mod inv input parameter"); + err = -EINVAL; + goto error; } + } else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_RSA) { + if (xform->rsa.n.length == 0) { + QAT_LOG(ERR, "Invalid rsa input parameter"); + err = -EINVAL; + goto error; + } + } else if (xform->xform_type >= RTE_CRYPTO_ASYM_XFORM_TYPE_LIST_END + || xform->xform_type <= RTE_CRYPTO_ASYM_XFORM_NONE) { + QAT_LOG(ERR, "Invalid asymmetric crypto xform"); + err = -EINVAL; + goto error; + } else { + QAT_LOG(ERR, "Asymmetric crypto xform not implemented"); + err = -EINVAL; + goto error; } - return -1; -} -static inline void qat_fill_req_tmpl(struct icp_qat_fw_pke_request *qat_req) -{ - memset(qat_req, 0, sizeof(*qat_req)); - qat_req->pke_hdr.service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_PKE; + session->xform = xform; + qat_asym_build_req_tmpl(sess_private_data); + set_asym_session_private_data(sess, dev->driver_id, + sess_private_data); - qat_req->pke_hdr.hdr_flags = - ICP_QAT_FW_COMN_HDR_FLAGS_BUILD - (ICP_QAT_FW_COMN_REQ_FLAG_SET); + return 0; +error: + rte_mempool_put(mempool, sess_private_data); + return err; } -static inline void qat_asym_build_req_tmpl(void *sess_private_data) +unsigned int +qat_asym_session_get_private_size( + struct rte_cryptodev *dev __rte_unused) { - struct icp_qat_fw_pke_request *qat_req; - struct qat_asym_session *session = sess_private_data; - - qat_req = &session->req_tmpl; - qat_fill_req_tmpl(qat_req); + return RTE_ALIGN_CEIL(sizeof(struct qat_asym_session), 8); } -static size_t max_of(int n, ...) +void +qat_asym_session_clear(struct rte_cryptodev *dev, + struct rte_cryptodev_asym_session *sess) { - va_list args; - size_t len = 0, num; - int i; + uint8_t index = dev->driver_id; + void *sess_priv = get_asym_session_private_data(sess, index); + struct qat_asym_session *s = (struct qat_asym_session *)sess_priv; - va_start(args, n); - len = va_arg(args, size_t); + if (sess_priv) { + memset(s, 0, qat_asym_session_get_private_size(dev)); + struct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv); - for (i = 0; i < n - 1; i++) { - num = va_arg(args, size_t); - if (num > len) - len = num; + set_asym_session_private_data(sess, index, NULL); + rte_mempool_put(sess_mp, sess_priv); } - va_end(args); - - return len; } +/* An rte_driver is needed in the registration of both the device and the driver + * with cryptodev. + * The actual qat pci's rte_driver can't be used as its name represents + * the whole pci device with all services. Think of this as a holder for a name + * for the crypto part of the pci device. + */ +static const char qat_asym_drv_name[] = RTE_STR(CRYPTODEV_NAME_QAT_ASYM_PMD); +static const struct rte_driver cryptodev_qat_asym_driver = { + .name = qat_asym_drv_name, + .alias = qat_asym_drv_name +}; + + static void qat_clear_arrays(struct qat_asym_op_cookie *cookie, int in_count, int out_count, int alg_size) { @@ -106,7 +152,230 @@ static void qat_clear_arrays_by_alg(struct qat_asym_op_cookie *cookie, } } -static int qat_asym_check_nonzero(rte_crypto_param n) +static void qat_asym_collect_response(struct rte_crypto_op *rx_op, + struct qat_asym_op_cookie *cookie, + struct rte_crypto_asym_xform *xform) +{ + size_t alg_size, alg_size_in_bytes = 0; + struct rte_crypto_asym_op *asym_op = rx_op->asym; + + if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODEX) { + rte_crypto_param n = xform->modex.modulus; + + alg_size = cookie->alg_size; + alg_size_in_bytes = alg_size >> 3; + uint8_t *modexp_result = asym_op->modex.result.data; + + if (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED) { + rte_memcpy(modexp_result + + (asym_op->modex.result.length - + n.length), + cookie->output_array[0] + alg_size_in_bytes + - n.length, n.length + ); + rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS; +#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG + QAT_DP_HEXDUMP_LOG(DEBUG, "ModExp result", + cookie->output_array[0], + alg_size_in_bytes); + +#endif + } + } else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODINV) { + rte_crypto_param n = xform->modinv.modulus; + + alg_size = cookie->alg_size; + alg_size_in_bytes = alg_size >> 3; + uint8_t *modinv_result = asym_op->modinv.result.data; + + if (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED) { + rte_memcpy(modinv_result + + (asym_op->modinv.result.length + - n.length), + cookie->output_array[0] + alg_size_in_bytes + - n.length, n.length); + rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS; +#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG + QAT_DP_HEXDUMP_LOG(DEBUG, "ModInv result", + cookie->output_array[0], + alg_size_in_bytes); +#endif + } + } else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_RSA) { + + alg_size = cookie->alg_size; + alg_size_in_bytes = alg_size >> 3; + if (asym_op->rsa.op_type == RTE_CRYPTO_ASYM_OP_ENCRYPT || + asym_op->rsa.op_type == + RTE_CRYPTO_ASYM_OP_VERIFY) { + if (asym_op->rsa.op_type == + RTE_CRYPTO_ASYM_OP_ENCRYPT) { + uint8_t *rsa_result = asym_op->rsa.cipher.data; + + rte_memcpy(rsa_result, + cookie->output_array[0], + alg_size_in_bytes); + rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS; +#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG + QAT_DP_HEXDUMP_LOG(DEBUG, "RSA Encrypted data", + cookie->output_array[0], + alg_size_in_bytes); +#endif + } else if (asym_op->rsa.op_type == + RTE_CRYPTO_ASYM_OP_VERIFY) { + uint8_t *rsa_result = asym_op->rsa.cipher.data; + + switch (asym_op->rsa.pad) { + case RTE_CRYPTO_RSA_PADDING_NONE: + rte_memcpy(rsa_result, + cookie->output_array[0], + alg_size_in_bytes); + rx_op->status = + RTE_CRYPTO_OP_STATUS_SUCCESS; +#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG + QAT_DP_HEXDUMP_LOG(DEBUG, "RSA Signature", + cookie->output_array[0], + alg_size_in_bytes); +#endif + break; + default: + QAT_LOG(ERR, "Padding not supported"); + rx_op->status = + RTE_CRYPTO_OP_STATUS_ERROR; + break; + } + } + } else { + if (asym_op->rsa.op_type == + RTE_CRYPTO_ASYM_OP_DECRYPT) { + uint8_t *rsa_result = asym_op->rsa.message.data; + + switch (asym_op->rsa.pad) { + case RTE_CRYPTO_RSA_PADDING_NONE: + rte_memcpy(rsa_result, + cookie->output_array[0], + alg_size_in_bytes); + rx_op->status = + RTE_CRYPTO_OP_STATUS_SUCCESS; + break; + default: + QAT_LOG(ERR, "Padding not supported"); + rx_op->status = + RTE_CRYPTO_OP_STATUS_ERROR; + break; + } +#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG + QAT_DP_HEXDUMP_LOG(DEBUG, "RSA Decrypted Message", + rsa_result, alg_size_in_bytes); +#endif + } else if (asym_op->rsa.op_type == + RTE_CRYPTO_ASYM_OP_SIGN) { + uint8_t *rsa_result = asym_op->rsa.sign.data; + + rte_memcpy(rsa_result, + cookie->output_array[0], + alg_size_in_bytes); + rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS; +#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG + QAT_DP_HEXDUMP_LOG(DEBUG, "RSA Signature", + cookie->output_array[0], + alg_size_in_bytes); +#endif + } + } + } + qat_clear_arrays_by_alg(cookie, xform, alg_size_in_bytes); +} + +int +qat_asym_process_response(void __rte_unused * *op, uint8_t *resp, + void *op_cookie, __rte_unused uint64_t *dequeue_err_count) +{ + struct qat_asym_session *ctx; + struct icp_qat_fw_pke_resp *resp_msg = + (struct icp_qat_fw_pke_resp *)resp; + struct rte_crypto_op *rx_op = (struct rte_crypto_op *)(uintptr_t) + (resp_msg->opaque); + struct qat_asym_op_cookie *cookie = op_cookie; + + if (cookie->error) { + cookie->error = 0; + if (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED) + rx_op->status = RTE_CRYPTO_OP_STATUS_ERROR; + QAT_DP_LOG(ERR, "Cookie status returned error"); + } else { + if (ICP_QAT_FW_PKE_RESP_PKE_STAT_GET( + resp_msg->pke_resp_hdr.resp_status.pke_resp_flags)) { + if (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED) + rx_op->status = RTE_CRYPTO_OP_STATUS_ERROR; + QAT_DP_LOG(ERR, "Asymmetric response status" + " returned error"); + } + if (resp_msg->pke_resp_hdr.resp_status.comn_err_code) { + if (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED) + rx_op->status = RTE_CRYPTO_OP_STATUS_ERROR; + QAT_DP_LOG(ERR, "Asymmetric common status" + " returned error"); + } + } + + if (rx_op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) { + ctx = (struct qat_asym_session *)get_asym_session_private_data( + rx_op->asym->session, qat_asym_driver_id); + qat_asym_collect_response(rx_op, cookie, ctx->xform); + } else if (rx_op->sess_type == RTE_CRYPTO_OP_SESSIONLESS) { + qat_asym_collect_response(rx_op, cookie, rx_op->asym->xform); + } + *op = rx_op; + +#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG + QAT_DP_HEXDUMP_LOG(DEBUG, "resp_msg:", resp_msg, + sizeof(struct icp_qat_fw_pke_resp)); +#endif + + return 1; +} + +#define qat_asym_sz_2param(arg) (arg, sizeof(arg)/sizeof(*arg)) + +static int +qat_asym_get_sz_and_func_id(const uint32_t arr[][2], + size_t arr_sz, size_t *size, uint32_t *func_id) +{ + size_t i; + + for (i = 0; i < arr_sz; i++) { + if (*size <= arr[i][0]) { + *size = arr[i][0]; + *func_id = arr[i][1]; + return 0; + } + } + return -1; +} + +static size_t +max_of(int n, ...) +{ + va_list args; + size_t len = 0, num; + int i; + + va_start(args, n); + len = va_arg(args, size_t); + + for (i = 0; i < n - 1; i++) { + num = va_arg(args, size_t); + if (num > len) + len = num; + } + va_end(args); + + return len; +} + +static int +qat_asym_check_nonzero(rte_crypto_param n) { if (n.length < 8) { /* Not a case for any cryptograpic function except for DH @@ -545,263 +813,7 @@ qat_asym_build_request(void *in_op, return 0; } -static void qat_asym_collect_response(struct rte_crypto_op *rx_op, - struct qat_asym_op_cookie *cookie, - struct rte_crypto_asym_xform *xform) -{ - size_t alg_size, alg_size_in_bytes = 0; - struct rte_crypto_asym_op *asym_op = rx_op->asym; - - if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODEX) { - rte_crypto_param n = xform->modex.modulus; - - alg_size = cookie->alg_size; - alg_size_in_bytes = alg_size >> 3; - uint8_t *modexp_result = asym_op->modex.result.data; - - if (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED) { - rte_memcpy(modexp_result + - (asym_op->modex.result.length - - n.length), - cookie->output_array[0] + alg_size_in_bytes - - n.length, n.length - ); - rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS; -#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG - QAT_DP_HEXDUMP_LOG(DEBUG, "ModExp result", - cookie->output_array[0], - alg_size_in_bytes); - -#endif - } - } else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODINV) { - rte_crypto_param n = xform->modinv.modulus; - - alg_size = cookie->alg_size; - alg_size_in_bytes = alg_size >> 3; - uint8_t *modinv_result = asym_op->modinv.result.data; - - if (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED) { - rte_memcpy(modinv_result + (asym_op->modinv.result.length - - n.length), - cookie->output_array[0] + alg_size_in_bytes - - n.length, n.length); - rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS; -#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG - QAT_DP_HEXDUMP_LOG(DEBUG, "ModInv result", - cookie->output_array[0], - alg_size_in_bytes); -#endif - } - } else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_RSA) { - - alg_size = cookie->alg_size; - alg_size_in_bytes = alg_size >> 3; - if (asym_op->rsa.op_type == RTE_CRYPTO_ASYM_OP_ENCRYPT || - asym_op->rsa.op_type == - RTE_CRYPTO_ASYM_OP_VERIFY) { - if (asym_op->rsa.op_type == - RTE_CRYPTO_ASYM_OP_ENCRYPT) { - uint8_t *rsa_result = asym_op->rsa.cipher.data; - - rte_memcpy(rsa_result, - cookie->output_array[0], - alg_size_in_bytes); - rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS; -#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG - QAT_DP_HEXDUMP_LOG(DEBUG, "RSA Encrypted data", - cookie->output_array[0], - alg_size_in_bytes); -#endif - } else if (asym_op->rsa.op_type == - RTE_CRYPTO_ASYM_OP_VERIFY) { - uint8_t *rsa_result = asym_op->rsa.cipher.data; - - switch (asym_op->rsa.pad) { - case RTE_CRYPTO_RSA_PADDING_NONE: - rte_memcpy(rsa_result, - cookie->output_array[0], - alg_size_in_bytes); - rx_op->status = - RTE_CRYPTO_OP_STATUS_SUCCESS; -#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG - QAT_DP_HEXDUMP_LOG(DEBUG, "RSA Signature", - cookie->output_array[0], - alg_size_in_bytes); -#endif - break; - default: - QAT_LOG(ERR, "Padding not supported"); - rx_op->status = - RTE_CRYPTO_OP_STATUS_ERROR; - break; - } - } - } else { - if (asym_op->rsa.op_type == - RTE_CRYPTO_ASYM_OP_DECRYPT) { - uint8_t *rsa_result = asym_op->rsa.message.data; - - switch (asym_op->rsa.pad) { - case RTE_CRYPTO_RSA_PADDING_NONE: - rte_memcpy(rsa_result, - cookie->output_array[0], - alg_size_in_bytes); - rx_op->status = - RTE_CRYPTO_OP_STATUS_SUCCESS; - break; - default: - QAT_LOG(ERR, "Padding not supported"); - rx_op->status = - RTE_CRYPTO_OP_STATUS_ERROR; - break; - } -#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG - QAT_DP_HEXDUMP_LOG(DEBUG, "RSA Decrypted Message", - rsa_result, alg_size_in_bytes); -#endif - } else if (asym_op->rsa.op_type == RTE_CRYPTO_ASYM_OP_SIGN) { - uint8_t *rsa_result = asym_op->rsa.sign.data; - - rte_memcpy(rsa_result, - cookie->output_array[0], - alg_size_in_bytes); - rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS; -#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG - QAT_DP_HEXDUMP_LOG(DEBUG, "RSA Signature", - cookie->output_array[0], - alg_size_in_bytes); -#endif - } - } - } - qat_clear_arrays_by_alg(cookie, xform, alg_size_in_bytes); -} - -void -qat_asym_process_response(void **op, uint8_t *resp, - void *op_cookie) -{ - struct qat_asym_session *ctx; - struct icp_qat_fw_pke_resp *resp_msg = - (struct icp_qat_fw_pke_resp *)resp; - struct rte_crypto_op *rx_op = (struct rte_crypto_op *)(uintptr_t) - (resp_msg->opaque); - struct qat_asym_op_cookie *cookie = op_cookie; - - if (cookie->error) { - cookie->error = 0; - if (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED) - rx_op->status = RTE_CRYPTO_OP_STATUS_ERROR; - QAT_DP_LOG(ERR, "Cookie status returned error"); - } else { - if (ICP_QAT_FW_PKE_RESP_PKE_STAT_GET( - resp_msg->pke_resp_hdr.resp_status.pke_resp_flags)) { - if (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED) - rx_op->status = RTE_CRYPTO_OP_STATUS_ERROR; - QAT_DP_LOG(ERR, "Asymmetric response status" - " returned error"); - } - if (resp_msg->pke_resp_hdr.resp_status.comn_err_code) { - if (rx_op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED) - rx_op->status = RTE_CRYPTO_OP_STATUS_ERROR; - QAT_DP_LOG(ERR, "Asymmetric common status" - " returned error"); - } - } - - if (rx_op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) { - ctx = (struct qat_asym_session *)get_asym_session_private_data( - rx_op->asym->session, qat_asym_driver_id); - qat_asym_collect_response(rx_op, cookie, ctx->xform); - } else if (rx_op->sess_type == RTE_CRYPTO_OP_SESSIONLESS) { - qat_asym_collect_response(rx_op, cookie, rx_op->asym->xform); - } - *op = rx_op; - -#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG - QAT_DP_HEXDUMP_LOG(DEBUG, "resp_msg:", resp_msg, - sizeof(struct icp_qat_fw_pke_resp)); -#endif -} - -int -qat_asym_session_configure(struct rte_cryptodev *dev, - struct rte_crypto_asym_xform *xform, - struct rte_cryptodev_asym_session *sess, - struct rte_mempool *mempool) -{ - int err = 0; - void *sess_private_data; - struct qat_asym_session *session; - - if (rte_mempool_get(mempool, &sess_private_data)) { - QAT_LOG(ERR, - "Couldn't get object from session mempool"); - return -ENOMEM; - } - - session = sess_private_data; - if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODEX) { - if (xform->modex.exponent.length == 0 || - xform->modex.modulus.length == 0) { - QAT_LOG(ERR, "Invalid mod exp input parameter"); - err = -EINVAL; - goto error; - } - } else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_MODINV) { - if (xform->modinv.modulus.length == 0) { - QAT_LOG(ERR, "Invalid mod inv input parameter"); - err = -EINVAL; - goto error; - } - } else if (xform->xform_type == RTE_CRYPTO_ASYM_XFORM_RSA) { - if (xform->rsa.n.length == 0) { - QAT_LOG(ERR, "Invalid rsa input parameter"); - err = -EINVAL; - goto error; - } - } else if (xform->xform_type >= RTE_CRYPTO_ASYM_XFORM_TYPE_LIST_END - || xform->xform_type <= RTE_CRYPTO_ASYM_XFORM_NONE) { - QAT_LOG(ERR, "Invalid asymmetric crypto xform"); - err = -EINVAL; - goto error; - } else { - QAT_LOG(ERR, "Asymmetric crypto xform not implemented"); - err = -EINVAL; - goto error; - } - - session->xform = xform; - qat_asym_build_req_tmpl(sess_private_data); - set_asym_session_private_data(sess, dev->driver_id, - sess_private_data); - - return 0; -error: - rte_mempool_put(mempool, sess_private_data); - return err; -} - -unsigned int qat_asym_session_get_private_size( - struct rte_cryptodev *dev __rte_unused) -{ - return RTE_ALIGN_CEIL(sizeof(struct qat_asym_session), 8); -} - -void -qat_asym_session_clear(struct rte_cryptodev *dev, - struct rte_cryptodev_asym_session *sess) -{ - uint8_t index = dev->driver_id; - void *sess_priv = get_asym_session_private_data(sess, index); - struct qat_asym_session *s = (struct qat_asym_session *)sess_priv; - - if (sess_priv) { - memset(s, 0, qat_asym_session_get_private_size(dev)); - struct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv); - - set_asym_session_private_data(sess, index, NULL); - rte_mempool_put(sess_mp, sess_priv); - } -} +static struct cryptodev_driver qat_crypto_drv; +RTE_PMD_REGISTER_CRYPTO_DRIVER(qat_crypto_drv, + cryptodev_qat_asym_driver, + qat_asym_driver_id); Checking patch drivers/common/qat/meson.build... error: while searching for: endif if qat_crypto foreach f: ['qat_sym_pmd.c', 'qat_sym.c', 'qat_sym_session.c', 'qat_sym_hw_dp.c', 'qat_asym_pmd.c', 'qat_asym.c', 'qat_crypto.c', 'dev/qat_sym_pmd_gen1.c', 'dev/qat_asym_pmd_gen1.c', error: patch failed: drivers/common/qat/meson.build:70 Checking patch drivers/common/qat/qat_device.c... Checking patch drivers/common/qat/qat_qp.c... error: drivers/common/qat/qat_qp.c: does not match index Checking patch drivers/crypto/qat/qat_sym.c... error: drivers/crypto/qat/qat_sym.c: does not match index Checking patch drivers/crypto/qat/qat_sym.h... Checking patch drivers/crypto/qat/qat_sym_hw_dp.c... Checking patch drivers/crypto/qat/qat_sym_pmd.c... error: drivers/crypto/qat/qat_sym_pmd.c: does not match index Checking patch drivers/crypto/qat/qat_sym_pmd.h... error: while searching for: /* SPDX-License-Identifier: BSD-3-Clause * Copyright(c) 2015-2018 Intel Corporation */ #ifndef _QAT_SYM_PMD_H_ #define _QAT_SYM_PMD_H_ #ifdef BUILD_QAT_SYM #include #include #ifdef RTE_LIB_SECURITY #include #endif #include "qat_crypto.h" #include "qat_device.h" /** Intel(R) QAT Symmetric Crypto PMD driver name */ #define CRYPTODEV_NAME_QAT_SYM_PMD crypto_qat /* Internal capabilities */ #define QAT_SYM_CAP_MIXED_CRYPTO (1 << 0) #define QAT_SYM_CAP_VALID (1 << 31) /** * Macro to add a sym capability * helper function to add an sym capability * * **/ #define QAT_SYM_PLAIN_AUTH_CAP(n, b, d) \ { \ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, \ {.sym = { \ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, \ {.auth = { \ .algo = RTE_CRYPTO_AUTH_##n, \ b, d \ }, } \ }, } \ } #define QAT_SYM_AUTH_CAP(n, b, k, d, a, i) \ { \ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, \ {.sym = { \ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, \ {.auth = { \ .algo = RTE_CRYPTO_AUTH_##n, \ b, k, d, a, i \ }, } \ }, } \ } #define QAT_SYM_AEAD_CAP(n, b, k, d, a, i) \ { \ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, \ {.sym = { \ .xform_type = RTE_CRYPTO_SYM_XFORM_AEAD, \ {.aead = { \ .algo = RTE_CRYPTO_AEAD_##n, \ b, k, d, a, i \ }, } \ }, } \ } #define QAT_SYM_CIPHER_CAP(n, b, k, i) \ { \ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, \ {.sym = { \ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, \ {.cipher = { \ .algo = RTE_CRYPTO_CIPHER_##n, \ b, k, i \ }, } \ }, } \ } extern uint8_t qat_sym_driver_id; extern struct qat_crypto_gen_dev_ops qat_sym_gen_dev_ops[]; int qat_sym_dev_create(struct qat_pci_device *qat_pci_dev, struct qat_dev_cmd_param *qat_dev_cmd_param); int qat_sym_dev_destroy(struct qat_pci_device *qat_pci_dev); void qat_sym_init_op_cookie(void *op_cookie); #endif #endif /* _QAT_SYM_PMD_H_ */ error: patch failed: drivers/crypto/qat/qat_sym_pmd.h:1 error: removal patch leaves file contents error: drivers/crypto/qat/qat_sym_pmd.h: patch does not apply Checking patch drivers/crypto/qat/qat_sym_session.c... error: drivers/crypto/qat/qat_sym_session.c: does not match index Applying patch drivers/common/qat/meson.build with 1 reject... Rejected hunk #1. Applied patch drivers/common/qat/qat_device.c cleanly. Applied patch drivers/crypto/qat/qat_sym.h cleanly. Applied patch drivers/crypto/qat/qat_sym_hw_dp.c cleanly. diff a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build (rejected hunks) @@ -70,7 +70,7 @@ if qat_compress endif if qat_crypto - foreach f: ['qat_sym_pmd.c', 'qat_sym.c', 'qat_sym_session.c', + foreach f: ['qat_sym.c', 'qat_sym_session.c', 'qat_sym_hw_dp.c', 'qat_asym_pmd.c', 'qat_asym.c', 'qat_crypto.c', 'dev/qat_sym_pmd_gen1.c', 'dev/qat_asym_pmd_gen1.c', Checking patch drivers/common/qat/meson.build... error: while searching for: if qat_crypto foreach f: ['qat_sym.c', 'qat_sym_session.c', 'qat_sym_hw_dp.c', 'qat_asym_pmd.c', 'qat_asym.c', 'qat_crypto.c', 'dev/qat_sym_pmd_gen1.c', 'dev/qat_asym_pmd_gen1.c', 'dev/qat_crypto_pmd_gen2.c', error: patch failed: drivers/common/qat/meson.build:71 Checking patch drivers/crypto/qat/qat_asym.c... error: drivers/crypto/qat/qat_asym.c: does not match index Checking patch drivers/crypto/qat/qat_asym_pmd.c... error: drivers/crypto/qat/qat_asym_pmd.c: does not match index Checking patch drivers/crypto/qat/qat_asym_pmd.h... error: while searching for: /* SPDX-License-Identifier: BSD-3-Clause * Copyright(c) 2019 Intel Corporation */ #ifndef _QAT_ASYM_PMD_H_ #define _QAT_ASYM_PMD_H_ #include #include "qat_crypto.h" #include "qat_device.h" /** Intel(R) QAT Asymmetric Crypto PMD driver name */ #define CRYPTODEV_NAME_QAT_ASYM_PMD crypto_qat_asym /** * Helper function to add an asym capability * **/ #define QAT_ASYM_CAP(n, o, l, r, i) \ { \ .op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC, \ {.asym = { \ .xform_capa = { \ .xform_type = RTE_CRYPTO_ASYM_XFORM_##n,\ .op_types = o, \ { \ .modlen = { \ .min = l, \ .max = r, \ .increment = i \ }, } \ } \ }, \ } \ } extern uint8_t qat_asym_driver_id; extern struct qat_crypto_gen_dev_ops qat_asym_gen_dev_ops[]; void qat_asym_init_op_cookie(void *op_cookie); uint16_t qat_asym_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops, uint16_t nb_ops); uint16_t qat_asym_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops, uint16_t nb_ops); #endif /* _QAT_ASYM_PMD_H_ */ error: patch failed: drivers/crypto/qat/qat_asym_pmd.h:1 error: removal patch leaves file contents error: drivers/crypto/qat/qat_asym_pmd.h: patch does not apply Applying patch drivers/common/qat/meson.build with 1 reject... Rejected hunk #1. diff a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build (rejected hunks) @@ -71,7 +71,7 @@ endif if qat_crypto foreach f: ['qat_sym.c', 'qat_sym_session.c', - 'qat_sym_hw_dp.c', 'qat_asym_pmd.c', 'qat_asym.c', 'qat_crypto.c', + 'qat_sym_hw_dp.c', 'qat_asym.c', 'qat_crypto.c', 'dev/qat_sym_pmd_gen1.c', 'dev/qat_asym_pmd_gen1.c', 'dev/qat_crypto_pmd_gen2.c', Checking patch drivers/common/qat/qat_qp.c... error: drivers/common/qat/qat_qp.c: does not match index Checking patch drivers/common/qat/qat_qp.h... error: drivers/common/qat/qat_qp.h: does not match index Checking patch drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c... error: drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c: does not exist in index Checking patch drivers/crypto/qat/dev/qat_sym_pmd_gen1.c... error: drivers/crypto/qat/dev/qat_sym_pmd_gen1.c: does not exist in index Checking patch drivers/crypto/qat/qat_asym.c... error: drivers/crypto/qat/qat_asym.c: does not match index Checking patch drivers/crypto/qat/qat_asym.h... error: drivers/crypto/qat/qat_asym.h: does not match index Checking patch drivers/crypto/qat/qat_crypto.h... error: drivers/crypto/qat/qat_crypto.h: does not exist in index Checking patch drivers/crypto/qat/qat_sym.c... error: drivers/crypto/qat/qat_sym.c: does not match index Checking patch drivers/crypto/qat/qat_sym.h... error: drivers/crypto/qat/qat_sym.h: does not match index Checking patch drivers/crypto/qat/qat_sym_session.c... error: drivers/crypto/qat/qat_sym_session.c: does not match index Checking patch drivers/crypto/qat/qat_sym_session.h... error: drivers/crypto/qat/qat_sym_session.h: does not match index Checking patch drivers/compress/qat/qat_comp_pmd.c... error: drivers/compress/qat/qat_comp_pmd.c: does not match index Checking patch drivers/common/qat/meson.build... error: while searching for: if qat_crypto foreach f: ['qat_sym.c', 'qat_sym_session.c', 'qat_sym_hw_dp.c', 'qat_asym.c', 'qat_crypto.c', 'dev/qat_sym_pmd_gen1.c', 'dev/qat_asym_pmd_gen1.c', 'dev/qat_crypto_pmd_gen2.c', error: patch failed: drivers/common/qat/meson.build:71 Checking patch drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c... error: drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c: does not exist in index Checking patch drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c... error: drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c: does not exist in index Checking patch drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c... error: drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c: does not exist in index Checking patch drivers/crypto/qat/dev/qat_crypto_pmd_gens.h... error: drivers/crypto/qat/dev/qat_crypto_pmd_gens.h: does not exist in index Checking patch drivers/crypto/qat/dev/qat_sym_pmd_gen1.c... error: drivers/crypto/qat/dev/qat_sym_pmd_gen1.c: does not exist in index Checking patch drivers/crypto/qat/qat_crypto.h... error: drivers/crypto/qat/qat_crypto.h: does not exist in index Checking patch drivers/crypto/qat/qat_sym.c... error: drivers/crypto/qat/qat_sym.c: does not match index Checking patch drivers/crypto/qat/qat_sym_hw_dp.c... error: drivers/crypto/qat/qat_sym_hw_dp.c: does not match index Applying patch drivers/common/qat/meson.build with 1 reject... Rejected hunk #1. diff a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build (rejected hunks) @@ -71,7 +71,7 @@ endif if qat_crypto foreach f: ['qat_sym.c', 'qat_sym_session.c', - 'qat_sym_hw_dp.c', 'qat_asym.c', 'qat_crypto.c', + 'qat_asym.c', 'qat_crypto.c', 'dev/qat_sym_pmd_gen1.c', 'dev/qat_asym_pmd_gen1.c', 'dev/qat_crypto_pmd_gen2.c', Checking patch drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c... error: drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c: does not exist in index Checking patch drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c... error: drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c: does not exist in index Checking patch drivers/crypto/qat/dev/qat_sym_pmd_gen1.c... error: drivers/crypto/qat/dev/qat_sym_pmd_gen1.c: does not exist in index Checking patch app/test/test_cryptodev.c... error: while searching for: int enqueue_status, dequeue_status; struct crypto_unittest_params *ut_params = &unittest_params; int is_sgl = sop->m_src->nb_segs > 1; ctx_service_size = rte_cryptodev_get_raw_dp_ctx_size(dev_id); if (ctx_service_size < 0) { error: patch failed: app/test/test_cryptodev.c:209 Hunk #2 succeeded at 240 (offset -8 lines). error: while searching for: if (is_sgl) { uint32_t remaining_off = auth_offset + auth_len; struct rte_mbuf *sgl_buf = sop->m_src; while (remaining_off >= rte_pktmbuf_data_len(sgl_buf) && sgl_buf->next != NULL) { error: patch failed: app/test/test_cryptodev.c:277 error: while searching for: /* Then check if digest-encrypted conditions are met */ if ((auth_offset + auth_len < cipher_offset + cipher_len) && (digest.iova == auth_end_iova) && is_sgl) max_len = RTE_MAX(max_len, auth_offset + auth_len + ut_params->auth_xform.auth.digest_length); } else if (is_cipher) { error: patch failed: app/test/test_cryptodev.c:293 Hunk #5 succeeded at 330 (offset -33 lines). Hunk #6 succeeded at 4080 (offset -29 lines). Hunk #7 succeeded at 7313 (offset -29 lines). Hunk #8 succeeded at 7374 (offset -29 lines). Applying patch app/test/test_cryptodev.c with 3 rejects... Rejected hunk #1. Hunk #2 applied cleanly. Rejected hunk #3. Rejected hunk #4. Hunk #5 applied cleanly. Hunk #6 applied cleanly. Hunk #7 applied cleanly. Hunk #8 applied cleanly. diff a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c (rejected hunks) @@ -209,6 +209,7 @@ process_sym_raw_dp_op(uint8_t dev_id, uint16_t qp_id, int enqueue_status, dequeue_status; struct crypto_unittest_params *ut_params = &unittest_params; int is_sgl = sop->m_src->nb_segs > 1; + int is_oop = 0; ctx_service_size = rte_cryptodev_get_raw_dp_ctx_size(dev_id); if (ctx_service_size < 0) { @@ -277,6 +281,8 @@ process_sym_raw_dp_op(uint8_t dev_id, uint16_t qp_id, if (is_sgl) { uint32_t remaining_off = auth_offset + auth_len; struct rte_mbuf *sgl_buf = sop->m_src; + if (is_oop) + sgl_buf = sop->m_dst; while (remaining_off >= rte_pktmbuf_data_len(sgl_buf) && sgl_buf->next != NULL) { @@ -293,7 +299,8 @@ process_sym_raw_dp_op(uint8_t dev_id, uint16_t qp_id, /* Then check if digest-encrypted conditions are met */ if ((auth_offset + auth_len < cipher_offset + cipher_len) && (digest.iova == auth_end_iova) && is_sgl) - max_len = RTE_MAX(max_len, auth_offset + auth_len + + max_len = RTE_MAX(max_len, + auth_offset + auth_len + ut_params->auth_xform.auth.digest_length); } else if (is_cipher) { https://lab.dpdk.org/results/dashboard/patchsets/20018/ UNH-IOL DPDK Community Lab