* |WARNING| pw110981 [PATCH v2 1/8] eal: add initial support for RISC-V architecture
[not found] <20220510150759.525434-2-kda@semihalf.com>
@ 2022-05-10 15:08 ` checkpatch
0 siblings, 0 replies; only message in thread
From: checkpatch @ 2022-05-10 15:08 UTC (permalink / raw)
To: test-report; +Cc: Stanislaw Kardach
Test-Label: checkpatch
Test-Status: WARNING
http://dpdk.org/patch/110981
_coding style issues_
WARNING:BAD_SIGN_OFF: Non-standard signature: Sponsored-by:
#133:
Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
WARNING:BAD_SIGN_OFF: Non-standard signature: Sponsored-by:
#134:
Sponsored-by: Sam Grove <sam.grove@sifive.com>
ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#812: FILE: lib/eal/riscv/include/rte_atomic.h:24:
+#define rte_mb() asm volatile("fence rw, rw" : : : "memory")
ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#814: FILE: lib/eal/riscv/include/rte_atomic.h:26:
+#define rte_wmb() asm volatile("fence w, w" : : : "memory")
ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#816: FILE: lib/eal/riscv/include/rte_atomic.h:28:
+#define rte_rmb() asm volatile("fence r, r" : : : "memory")
ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#824: FILE: lib/eal/riscv/include/rte_atomic.h:36:
+#define rte_io_mb() asm volatile("fence iorw, iorw" : : : "memory")
ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#826: FILE: lib/eal/riscv/include/rte_atomic.h:38:
+#define rte_io_wmb() asm volatile("fence orw, ow" : : : "memory")
ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#828: FILE: lib/eal/riscv/include/rte_atomic.h:40:
+#define rte_io_rmb() asm volatile("fence ir, ir" : : : "memory")
ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#978: FILE: lib/eal/riscv/include/rte_cycles.h:21:
+#define RV64_CSRR(reg, value) \
+ asm volatile("csrr %0, " #reg : "=r" (value) : : "memory")
WARNING:TYPO_SPELLING: 'hart' may be misspelled - perhaps 'heart'?
#1000: FILE: lib/eal/riscv/include/rte_cycles.h:43:
+/** Read hart cycle counter */
WARNING:TYPO_SPELLING: 'hart' may be misspelled - perhaps 'heart'?
#1009: FILE: lib/eal/riscv/include/rte_cycles.h:52:
+/** Read hart cycle counter ensuring no re-ordering */
total: 7 errors, 4 warnings, 1431 lines checked
Warning in lib/eal/riscv/include/rte_vect.h:
Using compiler attribute directly
Warning in lib/eal/riscv/include/rte_atomic.h:
Using rte_smp_[r/w]mb
Warning in lib/eal/riscv/include/rte_atomic.h:
Using __atomic_thread_fence
^ permalink raw reply [flat|nested] only message in thread
only message in thread, other threads:[~2022-05-10 15:08 UTC | newest]
Thread overview: (only message) (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <20220510150759.525434-2-kda@semihalf.com>
2022-05-10 15:08 ` |WARNING| pw110981 [PATCH v2 1/8] eal: add initial support for RISC-V architecture checkpatch
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).