From: checkpatch@dpdk.org
To: test-report@dpdk.org
Cc: Alex Vesker <valex@nvidia.com>
Subject: |WARNING| pw116676 [v1 12/19] net/mlx5/hws: Add HWS definer layer
Date: Thu, 22 Sep 2022 21:08:53 +0200 (CEST) [thread overview]
Message-ID: <20220922190853.B46B2121F02@dpdk.org> (raw)
In-Reply-To: <20220922190345.394-13-valex@nvidia.com>
Test-Label: checkpatch
Test-Status: WARNING
http://dpdk.org/patch/116676
_coding style issues_
WARNING:LONG_LINE_COMMENT: line length of 111 exceeds 100 columns
#144: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:2:
+ * Copyright (c) Copyright (c) 2022 NVIDIA Corporation 2021 NVIDIA CORPORATION. All rights reserved. Affiliates
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#164: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:22:
+#define _DR_SET_32(p, v, byte_off, bit_off, mask) \
+ do { \
+ u32 _v = v; \
+ *((rte_be32_t *)(p) + ((byte_off) / 4)) = \
+ rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
+ ((byte_off) / 4))) & \
+ (~((mask) << (bit_off)))) | \
+ (((_v) & (mask)) << \
+ (bit_off))); \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'byte_off' - possible side-effects?
#164: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:22:
+#define _DR_SET_32(p, v, byte_off, bit_off, mask) \
+ do { \
+ u32 _v = v; \
+ *((rte_be32_t *)(p) + ((byte_off) / 4)) = \
+ rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
+ ((byte_off) / 4))) & \
+ (~((mask) << (bit_off)))) | \
+ (((_v) & (mask)) << \
+ (bit_off))); \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'bit_off' - possible side-effects?
#164: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:22:
+#define _DR_SET_32(p, v, byte_off, bit_off, mask) \
+ do { \
+ u32 _v = v; \
+ *((rte_be32_t *)(p) + ((byte_off) / 4)) = \
+ rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
+ ((byte_off) / 4))) & \
+ (~((mask) << (bit_off)))) | \
+ (((_v) & (mask)) << \
+ (bit_off))); \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mask' - possible side-effects?
#164: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:22:
+#define _DR_SET_32(p, v, byte_off, bit_off, mask) \
+ do { \
+ u32 _v = v; \
+ *((rte_be32_t *)(p) + ((byte_off) / 4)) = \
+ rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
+ ((byte_off) / 4))) & \
+ (~((mask) << (bit_off)))) | \
+ (((_v) & (mask)) << \
+ (bit_off))); \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#176: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:34:
+#define DR_SET(p, v, byte_off, bit_off, mask) \
+ do { \
+ if (unlikely(bit_off < 0)) { \
+ u32 _bit_off = -1 * (bit_off); \
+ u32 second_dw_mask = mask & ((1 << _bit_off) - 1); \
+ _DR_SET_32(p, (v) >> _bit_off, byte_off, 0, mask >> _bit_off); \
+ _DR_SET_32(p, (v) & second_dw_mask, (byte_off) + DW_SIZE, \
+ (bit_off) % BITS_IN_DW, second_dw_mask); \
+ } else { \
+ _DR_SET_32(p, v, byte_off, bit_off, mask); \
+ } \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'v' - possible side-effects?
#176: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:34:
+#define DR_SET(p, v, byte_off, bit_off, mask) \
+ do { \
+ if (unlikely(bit_off < 0)) { \
+ u32 _bit_off = -1 * (bit_off); \
+ u32 second_dw_mask = mask & ((1 << _bit_off) - 1); \
+ _DR_SET_32(p, (v) >> _bit_off, byte_off, 0, mask >> _bit_off); \
+ _DR_SET_32(p, (v) & second_dw_mask, (byte_off) + DW_SIZE, \
+ (bit_off) % BITS_IN_DW, second_dw_mask); \
+ } else { \
+ _DR_SET_32(p, v, byte_off, bit_off, mask); \
+ } \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'byte_off' - possible side-effects?
#176: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:34:
+#define DR_SET(p, v, byte_off, bit_off, mask) \
+ do { \
+ if (unlikely(bit_off < 0)) { \
+ u32 _bit_off = -1 * (bit_off); \
+ u32 second_dw_mask = mask & ((1 << _bit_off) - 1); \
+ _DR_SET_32(p, (v) >> _bit_off, byte_off, 0, mask >> _bit_off); \
+ _DR_SET_32(p, (v) & second_dw_mask, (byte_off) + DW_SIZE, \
+ (bit_off) % BITS_IN_DW, second_dw_mask); \
+ } else { \
+ _DR_SET_32(p, v, byte_off, bit_off, mask); \
+ } \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'bit_off' - possible side-effects?
#176: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:34:
+#define DR_SET(p, v, byte_off, bit_off, mask) \
+ do { \
+ if (unlikely(bit_off < 0)) { \
+ u32 _bit_off = -1 * (bit_off); \
+ u32 second_dw_mask = mask & ((1 << _bit_off) - 1); \
+ _DR_SET_32(p, (v) >> _bit_off, byte_off, 0, mask >> _bit_off); \
+ _DR_SET_32(p, (v) & second_dw_mask, (byte_off) + DW_SIZE, \
+ (bit_off) % BITS_IN_DW, second_dw_mask); \
+ } else { \
+ _DR_SET_32(p, v, byte_off, bit_off, mask); \
+ } \
+ } while (0)
CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'bit_off' may be better as '(bit_off)' to avoid precedence issues
#176: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:34:
+#define DR_SET(p, v, byte_off, bit_off, mask) \
+ do { \
+ if (unlikely(bit_off < 0)) { \
+ u32 _bit_off = -1 * (bit_off); \
+ u32 second_dw_mask = mask & ((1 << _bit_off) - 1); \
+ _DR_SET_32(p, (v) >> _bit_off, byte_off, 0, mask >> _bit_off); \
+ _DR_SET_32(p, (v) & second_dw_mask, (byte_off) + DW_SIZE, \
+ (bit_off) % BITS_IN_DW, second_dw_mask); \
+ } else { \
+ _DR_SET_32(p, v, byte_off, bit_off, mask); \
+ } \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mask' - possible side-effects?
#176: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:34:
+#define DR_SET(p, v, byte_off, bit_off, mask) \
+ do { \
+ if (unlikely(bit_off < 0)) { \
+ u32 _bit_off = -1 * (bit_off); \
+ u32 second_dw_mask = mask & ((1 << _bit_off) - 1); \
+ _DR_SET_32(p, (v) >> _bit_off, byte_off, 0, mask >> _bit_off); \
+ _DR_SET_32(p, (v) & second_dw_mask, (byte_off) + DW_SIZE, \
+ (bit_off) % BITS_IN_DW, second_dw_mask); \
+ } else { \
+ _DR_SET_32(p, v, byte_off, bit_off, mask); \
+ } \
+ } while (0)
CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'mask' may be better as '(mask)' to avoid precedence issues
#176: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:34:
+#define DR_SET(p, v, byte_off, bit_off, mask) \
+ do { \
+ if (unlikely(bit_off < 0)) { \
+ u32 _bit_off = -1 * (bit_off); \
+ u32 second_dw_mask = mask & ((1 << _bit_off) - 1); \
+ _DR_SET_32(p, (v) >> _bit_off, byte_off, 0, mask >> _bit_off); \
+ _DR_SET_32(p, (v) & second_dw_mask, (byte_off) + DW_SIZE, \
+ (bit_off) % BITS_IN_DW, second_dw_mask); \
+ } else { \
+ _DR_SET_32(p, v, byte_off, bit_off, mask); \
+ } \
+ } while (0)
CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'byte_off' may be better as '(byte_off)' to avoid precedence issues
#190: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:48:
+#define DR_SET_BE32(p, v, byte_off, bit_off, mask) \
+ do { \
+ *((rte_be32_t *)((uint8_t *)(p) + byte_off)) = (v); \
+ } while (0)
WARNING:SINGLE_STATEMENT_DO_WHILE_MACRO: Single statement macros should not use a do {} while (0) loop
#190: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:48:
+#define DR_SET_BE32(p, v, byte_off, bit_off, mask) \
+ do { \
+ *((rte_be32_t *)((uint8_t *)(p) + byte_off)) = (v); \
+ } while (0)
CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'byte_off' may be better as '(byte_off)' to avoid precedence issues
#196: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:54:
+#define DR_SET_BE32P(p, v_ptr, byte_off, bit_off, mask) \
+ memcpy((uint8_t *)(p) + byte_off, v_ptr, 4);
WARNING:TRAILING_SEMICOLON: macros should not use a trailing semicolon
#196: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:54:
+#define DR_SET_BE32P(p, v_ptr, byte_off, bit_off, mask) \
+ memcpy((uint8_t *)(p) + byte_off, v_ptr, 4);
CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'byte_off' may be better as '(byte_off)' to avoid precedence issues
#200: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:58:
+#define DR_SET_BE16(p, v, byte_off, bit_off, mask) \
+ do { \
+ *((rte_be16_t *)((uint8_t *)(p) + byte_off)) = (v); \
+ } while (0)
WARNING:SINGLE_STATEMENT_DO_WHILE_MACRO: Single statement macros should not use a do {} while (0) loop
#200: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:58:
+#define DR_SET_BE16(p, v, byte_off, bit_off, mask) \
+ do { \
+ *((rte_be16_t *)((uint8_t *)(p) + byte_off)) = (v); \
+ } while (0)
CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'byte_off' may be better as '(byte_off)' to avoid precedence issues
#206: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:64:
+#define DR_SET_BE16P(p, v_ptr, byte_off, bit_off, mask) \
+ memcpy((uint8_t *)(p) + byte_off, v_ptr, 2);
WARNING:TRAILING_SEMICOLON: macros should not use a trailing semicolon
#206: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:64:
+#define DR_SET_BE16P(p, v_ptr, byte_off, bit_off, mask) \
+ memcpy((uint8_t *)(p) + byte_off, v_ptr, 2);
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'fc' - possible side-effects?
#213: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:71:
+#define DR_CALC_SET_HDR(fc, hdr, field) \
+ do { \
+ (fc)->bit_mask = __mlx5_mask(definer_hl, hdr.field); \
+ (fc)->bit_off = __mlx5_dw_bit_off(definer_hl, hdr.field); \
+ (fc)->byte_off = MLX5_BYTE_OFF(definer_hl, hdr.field); \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'hdr' - possible side-effects?
#213: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:71:
+#define DR_CALC_SET_HDR(fc, hdr, field) \
+ do { \
+ (fc)->bit_mask = __mlx5_mask(definer_hl, hdr.field); \
+ (fc)->bit_off = __mlx5_dw_bit_off(definer_hl, hdr.field); \
+ (fc)->byte_off = MLX5_BYTE_OFF(definer_hl, hdr.field); \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'field' - possible side-effects?
#213: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:71:
+#define DR_CALC_SET_HDR(fc, hdr, field) \
+ do { \
+ (fc)->bit_mask = __mlx5_mask(definer_hl, hdr.field); \
+ (fc)->bit_off = __mlx5_dw_bit_off(definer_hl, hdr.field); \
+ (fc)->byte_off = MLX5_BYTE_OFF(definer_hl, hdr.field); \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'fc' - possible side-effects?
#221: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:79:
+#define DR_CALC_SET(fc, hdr, field, is_inner) \
+ do { \
+ if (is_inner) { \
+ DR_CALC_SET_HDR(fc, hdr##_inner, field); \
+ } else { \
+ DR_CALC_SET_HDR(fc, hdr##_outer, field); \
+ } \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'field' - possible side-effects?
#221: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:79:
+#define DR_CALC_SET(fc, hdr, field, is_inner) \
+ do { \
+ if (is_inner) { \
+ DR_CALC_SET_HDR(fc, hdr##_inner, field); \
+ } else { \
+ DR_CALC_SET_HDR(fc, hdr##_outer, field); \
+ } \
+ } while (0)
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'typ' - possible side-effects?
#230: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:88:
+ #define DR_GET(typ, p, fld) \
+ ((rte_be_to_cpu_32(*((const rte_be32_t *)(p) + \
+ __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
+ __mlx5_mask(typ, fld))
CHECK:MACRO_ARG_REUSE: Macro argument reuse 'fld' - possible side-effects?
#230: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:88:
+ #define DR_GET(typ, p, fld) \
+ ((rte_be_to_cpu_32(*((const rte_be32_t *)(p) + \
+ __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
+ __mlx5_mask(typ, fld))
ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#256: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:114:
+#define LIST_OF_FIELDS_INFO \
+ X(SET_BE16, eth_type, v->type, rte_flow_item_eth) \
+ X(SET_BE32P, eth_smac_47_16, &v->src.addr_bytes[0], rte_flow_item_eth) \
+ X(SET_BE16P, eth_smac_15_0, &v->src.addr_bytes[4], rte_flow_item_eth) \
+ X(SET_BE32P, eth_dmac_47_16, &v->dst.addr_bytes[0], rte_flow_item_eth) \
+ X(SET_BE16P, eth_dmac_15_0, &v->dst.addr_bytes[4], rte_flow_item_eth) \
+ X(SET_BE16, tci, v->tci, rte_flow_item_vlan) \
+ X(SET, first_vlan_q, v->has_more_vlan ? STE_SVLAN : STE_CVLAN, rte_flow_item_vlan) \
+ X(SET, eth_first_vlan_q, v->has_vlan ? STE_CVLAN : 0, rte_flow_item_eth) \
+ X(SET, ipv4_ihl, v->ihl, rte_ipv4_hdr) \
+ X(SET, ipv4_tos, v->type_of_service, rte_ipv4_hdr) \
+ X(SET, ipv4_time_to_live, v->time_to_live, rte_ipv4_hdr) \
+ X(SET_BE32, ipv4_dst_addr, v->dst_addr, rte_ipv4_hdr) \
+ X(SET_BE32, ipv4_src_addr, v->src_addr, rte_ipv4_hdr) \
+ X(SET, ipv4_next_proto, v->next_proto_id, rte_ipv4_hdr) \
+ X(SET, ipv4_version, STE_IPV4, rte_ipv4_hdr) \
+ X(SET_BE16, ipv4_frag, v->fragment_offset, rte_ipv4_hdr) \
+ X(SET_BE16, ipv6_payload_len, v->hdr.payload_len, rte_flow_item_ipv6) \
+ X(SET, ipv6_proto, v->hdr.proto, rte_flow_item_ipv6) \
+ X(SET, ipv6_hop_limits, v->hdr.hop_limits, rte_flow_item_ipv6) \
+ X(SET_BE32P, ipv6_src_addr_127_96, &v->hdr.src_addr[0], rte_flow_item_ipv6) \
+ X(SET_BE32P, ipv6_src_addr_95_64, &v->hdr.src_addr[4], rte_flow_item_ipv6) \
+ X(SET_BE32P, ipv6_src_addr_63_32, &v->hdr.src_addr[8], rte_flow_item_ipv6) \
+ X(SET_BE32P, ipv6_src_addr_31_0, &v->hdr.src_addr[12], rte_flow_item_ipv6) \
+ X(SET_BE32P, ipv6_dst_addr_127_96, &v->hdr.dst_addr[0], rte_flow_item_ipv6) \
+ X(SET_BE32P, ipv6_dst_addr_95_64, &v->hdr.dst_addr[4], rte_flow_item_ipv6) \
+ X(SET_BE32P, ipv6_dst_addr_63_32, &v->hdr.dst_addr[8], rte_flow_item_ipv6) \
+ X(SET_BE32P, ipv6_dst_addr_31_0, &v->hdr.dst_addr[12], rte_flow_item_ipv6) \
+ X(SET, ipv6_version, STE_IPV6, rte_flow_item_ipv6) \
+ X(SET, ipv6_frag, v->has_frag_ext, rte_flow_item_ipv6) \
+ X(SET, icmp_protocol, STE_ICMP, rte_flow_item_icmp) \
+ X(SET, udp_protocol, STE_UDP, rte_flow_item_udp) \
+ X(SET_BE16, udp_src_port, v->hdr.src_port, rte_flow_item_udp) \
+ X(SET_BE16, udp_dst_port, v->hdr.dst_port, rte_flow_item_udp) \
+ X(SET, tcp_flags, v->hdr.tcp_flags, rte_flow_item_tcp) \
+ X(SET, tcp_protocol, STE_TCP, rte_flow_item_tcp) \
+ X(SET_BE16, tcp_src_port, v->hdr.src_port, rte_flow_item_tcp) \
+ X(SET_BE16, tcp_dst_port, v->hdr.dst_port, rte_flow_item_tcp) \
+ X(SET, gtp_udp_port, RTE_GTPU_UDP_PORT, rte_flow_item_gtp) \
+ X(SET_BE32, gtp_teid, v->teid, rte_flow_item_gtp) \
+ X(SET, gtp_msg_type, v->msg_type, rte_flow_item_gtp) \
+ X(SET, gtp_ext_flag, !!v->v_pt_rsv_flags, rte_flow_item_gtp) \
+ X(SET, gtp_next_ext_hdr, GTP_PDU_SC, rte_flow_item_gtp_psc) \
+ X(SET, vxlan_flags, v->flags, rte_flow_item_vxlan) \
+ X(SET, vxlan_udp_port, ETH_VXLAN_DEFAULT_PORT, rte_flow_item_vxlan) \
+ X(SET, tag, v->data, rte_flow_item_tag) \
+ X(SET, metadata, v->data, rte_flow_item_meta) \
+ X(SET_BE16, gre_c_ver, v->c_rsvd0_ver, rte_flow_item_gre) \
+ X(SET_BE16, gre_protocol_type, v->protocol, rte_flow_item_gre) \
+ X(SET, ipv4_protocol_gre, IPPROTO_GRE, rte_flow_item_gre) \
+ X(SET_BE32, gre_opt_key, v->key.key, rte_flow_item_gre_opt) \
+ X(SET_BE32, gre_opt_seq, v->sequence.sequence, rte_flow_item_gre_opt) \
+ X(SET_BE16, gre_opt_checksum, v->checksum_rsvd.checksum, rte_flow_item_gre_opt)
WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#263: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:121:
+ X(SET, first_vlan_q, v->has_more_vlan ? STE_SVLAN : STE_CVLAN, rte_flow_item_vlan) \
WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#308: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:166:
+ X(SET_BE16, gre_opt_checksum, v->checksum_rsvd.checksum, rte_flow_item_gre_opt)
CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'itme_type' may be better as '(itme_type)' to avoid precedence issues
#311: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:169:
+#define X(set_type, func_name, value, itme_type) \
+static void mlx5dr_definer_##func_name##_set( \
+ struct mlx5dr_definer_fc *fc, \
+ const void *item_spec, \
+ uint8_t *tag) \
+{ \
+ __rte_unused const struct itme_type *v = item_spec; \
+ DR_##set_type(tag, value, fc->byte_off, fc->bit_off, fc->bit_mask); \
+}
ERROR:SPACING: spaces required around that ':' (ctx:VxE)
#397: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:255:
+ ok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_IPV4_CSUM_OK):
^
ERROR:SPACING: spaces required around that ':' (ctx:VxE)
#407: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:265:
+ ok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_L4_CSUM_OK):
^
ERROR:SPACING: space required before the open parenthesis '('
#1089: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:947:
+ if(!fc->tag_set) {
ERROR:SPACING: space required before the open parenthesis '('
#1097: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:955:
+ if(!fc->tag_set) {
ERROR:SPACING: space required before the open parenthesis '('
#1316: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:1174:
+ if(!fc->tag_set) {
ERROR:SPACING: space required before the open parenthesis '('
#1368: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:1226:
+ if(!fc->tag_set) {
ERROR:CODE_INDENT: code indent should use tabs where possible
#1649: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:1507:
+ rte_errno = ENOMEM;$
WARNING:LEADING_SPACE: please, no spaces at the start of a line
#1649: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:1507:
+ rte_errno = ENOMEM;$
ERROR:CODE_INDENT: code indent should use tabs where possible
#1650: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:1508:
+ return rte_errno;$
WARNING:LEADING_SPACE: please, no spaces at the start of a line
#1650: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:1508:
+ return rte_errno;$
ERROR:CODE_INDENT: code indent should use tabs where possible
#1943: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:1801:
+ rte_errno = ENOMEM;$
WARNING:LEADING_SPACE: please, no spaces at the start of a line
#1943: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:1801:
+ rte_errno = ENOMEM;$
ERROR:CODE_INDENT: code indent should use tabs where possible
#1944: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:1802:
+ goto free_definer;$
WARNING:LEADING_SPACE: please, no spaces at the start of a line
#1944: FILE: drivers/net/mlx5/hws/mlx5dr_definer.c:1802:
+ goto free_definer;$
WARNING:LONG_LINE_COMMENT: line length of 111 exceeds 100 columns
#2016: FILE: drivers/net/mlx5/hws/mlx5dr_definer.h:2:
+ * Copyright (c) Copyright (c) 2022 NVIDIA Corporation 2021 NVIDIA CORPORATION. All rights reserved. Affiliates
ERROR:C99_COMMENTS: do not use C99 // comments
#2458: FILE: drivers/net/mlx5/hws/mlx5dr_definer.h:444:
+ // struct x udp_misc_outer; 0x20
ERROR:C99_COMMENTS: do not use C99 // comments
#2459: FILE: drivers/net/mlx5/hws/mlx5dr_definer.h:445:
+ // struct x udp_misc_inner; 0x20
ERROR:C99_COMMENTS: do not use C99 // comments
#2463: FILE: drivers/net/mlx5/hws/mlx5dr_definer.h:449:
+ // struct x mpls_outer; 0xa0
ERROR:C99_COMMENTS: do not use C99 // comments
#2464: FILE: drivers/net/mlx5/hws/mlx5dr_definer.h:450:
+ // struct x mpls_inner; 0xa0
ERROR:C99_COMMENTS: do not use C99 // comments
#2465: FILE: drivers/net/mlx5/hws/mlx5dr_definer.h:451:
+ // struct x config_headers_outer; 0x80
ERROR:C99_COMMENTS: do not use C99 // comments
#2466: FILE: drivers/net/mlx5/hws/mlx5dr_definer.h:452:
+ // struct x config_headers_inner; 0x80
ERROR:C99_COMMENTS: do not use C99 // comments
#2467: FILE: drivers/net/mlx5/hws/mlx5dr_definer.h:453:
+ // struct x random_number; 0x20
ERROR:C99_COMMENTS: do not use C99 // comments
#2468: FILE: drivers/net/mlx5/hws/mlx5dr_definer.h:454:
+ // struct x ipsec; 0x60
ERROR:C99_COMMENTS: do not use C99 // comments
#2471: FILE: drivers/net/mlx5/hws/mlx5dr_definer.h:457:
+ // struct x utc_timestamp; 0x40
ERROR:C99_COMMENTS: do not use C99 // comments
#2472: FILE: drivers/net/mlx5/hws/mlx5dr_definer.h:458:
+ // struct x free_running_timestamp; 0x40
ERROR:C99_COMMENTS: do not use C99 // comments
#2475: FILE: drivers/net/mlx5/hws/mlx5dr_definer.h:461:
+ // struct x ib_l3_extended;
ERROR:C99_COMMENTS: do not use C99 // comments
#2476: FILE: drivers/net/mlx5/hws/mlx5dr_definer.h:462:
+ // struct x rwh;
ERROR:C99_COMMENTS: do not use C99 // comments
#2477: FILE: drivers/net/mlx5/hws/mlx5dr_definer.h:463:
+ // struct x dcceth;
ERROR:C99_COMMENTS: do not use C99 // comments
#2478: FILE: drivers/net/mlx5/hws/mlx5dr_definer.h:464:
+ // struct x dceth;
ERROR:C99_COMMENTS: do not use C99 // comments
#2479: FILE: drivers/net/mlx5/hws/mlx5dr_definer.h:465:
+ // /.autodirect/swgwork/maayang/repo_1/golan_fw/include/
ERROR:C99_COMMENTS: do not use C99 // comments
#2480: FILE: drivers/net/mlx5/hws/mlx5dr_definer.h:466:
+ // tamar_g_cr_no_aligned_expose__descsteering_headers_layout_desc_adb.h
total: 27 errors, 12 warnings, 23 checks, 2448 lines checked
parent reply other threads:[~2022-09-22 19:08 UTC|newest]
Thread overview: expand[flat|nested] mbox.gz Atom feed
[parent not found: <20220922190345.394-13-valex@nvidia.com>]
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