* |WARNING| pw136499-136504 [PATCH v6 1/6] doc: fix fpga 5gnr configuration values
[not found] <20240207171350.242156-2-hernan.vargas@intel.com>
@ 2024-02-07 16:53 ` qemudev
2024-02-07 17:17 ` |SUCCESS| pw136499 " checkpatch
1 sibling, 0 replies; 2+ messages in thread
From: qemudev @ 2024-02-07 16:53 UTC (permalink / raw)
To: test-report; +Cc: Hernan Vargas, zhoumin
Test-Label: loongarch-compilation
Test-Status: WARNING
http://dpdk.org/patch/136499
_apply patch failure_
Submitter: Hernan Vargas <hernan.vargas@intel.com>
Date: Wed, 7 Feb 2024 09:13:45 -0800
DPDK git baseline: Repo:dpdk-next-baseband
Branch: for-main
CommitID: 263729efd1eb998ba1d7829971ecee620c79d0ce
Apply patch set 136499-136504 failed:
Checking patch drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h...
Checking patch drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c...
error: while searching for:
* Get HARQ buffer size for each VF/PF: When 0x00, there is no
* available DDR space for the corresponding VF/PF.
*/
reg_32 = fpga_reg_read_32(q->d->mmio_base,
FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS);
if (reg_32 < harq_in_length) {
left_length = reg_32;
rte_bbdev_log(ERR, "HARQ in length > HARQ buffer size\n");
}
input = (uint64_t *)rte_pktmbuf_mtod_offset(harq_input,
uint8_t *, in_offset);
while (left_length > 0) {
if (fpga_reg_read_8(q->d->mmio_base,
FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS) == 1) {
fpga_reg_write_32(q->d->mmio_base,
FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS,
out_offset);
fpga_reg_write_64(q->d->mmio_base,
FPGA_5GNR_FEC_DDR4_WR_DATA_REGS,
input[increment]);
left_length -= FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;
out_offset += FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;
increment++;
fpga_reg_write_8(q->d->mmio_base,
FPGA_5GNR_FEC_DDR4_WR_DONE_REGS, 1);
}
}
while (last_transaction > 0) {
if (fpga_reg_read_8(q->d->mmio_base,
FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS) == 1) {
fpga_reg_write_32(q->d->mmio_base,
FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS,
out_offset);
last_word = input[increment];
last_word &= (uint64_t)(1 << (last_transaction * 4))
- 1;
fpga_reg_write_64(q->d->mmio_base,
FPGA_5GNR_FEC_DDR4_WR_DATA_REGS,
last_word);
fpga_reg_write_8(q->d->mmio_base,
FPGA_5GNR_FEC_DDR4_WR_DONE_REGS, 1);
last_transaction = 0;
}
}
fpga_mutex_free(q);
return 1;
}
static inline int
fpga_harq_read_loopback(struct fpga_queue *q,
struct rte_mbuf *harq_output, uint16_t harq_in_length,
uint32_t harq_in_offset, uint32_t harq_out_offset)
{
fpga_mutex_acquisition(q);
uint32_t left_length, in_offset = harq_in_offset;
uint64_t reg;
uint32_t increment = 0;
uint64_t *input = NULL;
uint32_t last_transaction = harq_in_length
% FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;
if (last_transaction > 0)
harq_in_length += (8 - last_transaction);
reg = fpga_reg_read_32(q->d->mmio_base,
FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS);
if (reg < harq_in_length) {
harq_in_length = reg;
rte_bbdev_log(ERR, "HARQ in length > HARQ buffer size\n");
error: patch failed: drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c:1542
error: drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c: patch does not apply
Checking patch drivers/baseband/fpga_5gnr_fec/rte_pmd_fpga_5gnr_fec.h...
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