From: sys_stv@intel.com
To: test-report@dpdk.org, dts-test-report@dpdk.org
Subject: [dts-test-report] |WARNING| pw(106044) sid(21240) job(DTS_AUTO_412) [V3] test_plans: add test plan for cvl 1pps signal
Date: 18 Jan 2022 21:11:08 -0800 [thread overview]
Message-ID: <8ea9f5$k0tqsv@fmsmga001-auth.fm.intel.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 767 bytes --]
Test-Label: Intel-dts-suite-test
Test-Status: WARNING
http://dpdk.org/patch/106044
Subject: [V3] test_plans: add test plan for cvl 1pps signal
_SKIPPED_
Diff:
test_plans/index.rst
test_plans/cvl_1pps_signal_test_plan.rst
DPDK:
commit cadb255e25d690d719d6f159e0a63f8be60650a5
Author: Bruce Richardson <bruce.richardson@intel.com>
Date: Thu Dec 16 15:21:07 2021 +0000
Comment: eal: add OS defines for C conditional checks
DTS:
commit 889a137919cfa520fd7d52a3c42825e3d121b45d
Author: Wei Ling <weix.ling@intel.com>
Date: Fri Jan 14 16:18:49 2022 +0800
Comment: test_plans/*:modify dpdk app name
Platform 1: 10.239.251.107
OS: UB2004-64+216
Category: CVL Only | NIC PF | Virtio | NIC VF
Nic: fortville_spirit | columbiaville_25g
DPDK STV team
reply other threads:[~2022-01-19 5:11 UTC|newest]
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