* [dpdk-users] Segmentation fault at rte_cpu_get_flag_enabled
@ 2020-04-20 7:09 vikram T
2020-04-20 15:07 ` Stephen Hemminger
0 siblings, 1 reply; 4+ messages in thread
From: vikram T @ 2020-04-20 7:09 UTC (permalink / raw)
To: users
Hi,
I have been seeing the application crashes( DPDK v19.08) with segmentation
fault as below:
(gdb) bt
#0 0x000000000054fda9 in rte_cpu_get_flag_enabled ()
#1 0x00000000004f5d5e in rte_hash_crc_init_alg ()
#2 0x000000000084cf7d in __libc_csu_init ()
#3 0x00007ffff4df9425 in __libc_start_main () from /lib64/libc.so.6
#4 0x00000000005048df in _start ()
(gdb) q
Here the DPDK is built and linked on the machine different from the target
machine.
Hence used the flag - "CONFIG_RTE_MACHINE = default" but no success.
Is there anything that needs to be followed to overcome this blocking issue?
Regards
Vikram
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [dpdk-users] Segmentation fault at rte_cpu_get_flag_enabled
2020-04-20 7:09 [dpdk-users] Segmentation fault at rte_cpu_get_flag_enabled vikram T
@ 2020-04-20 15:07 ` Stephen Hemminger
2020-04-20 18:03 ` vikram T
0 siblings, 1 reply; 4+ messages in thread
From: Stephen Hemminger @ 2020-04-20 15:07 UTC (permalink / raw)
To: vikram T; +Cc: users
On Mon, 20 Apr 2020 12:39:02 +0530
vikram T <vikramet@gmail.com> wrote:
> Hi,
> I have been seeing the application crashes( DPDK v19.08) with segmentation
> fault as below:
> (gdb) bt
> #0 0x000000000054fda9 in rte_cpu_get_flag_enabled ()
> #1 0x00000000004f5d5e in rte_hash_crc_init_alg ()
> #2 0x000000000084cf7d in __libc_csu_init ()
> #3 0x00007ffff4df9425 in __libc_start_main () from /lib64/libc.so.6
> #4 0x00000000005048df in _start ()
> (gdb) q
>
> Here the DPDK is built and linked on the machine different from the target
> machine.
> Hence used the flag - "CONFIG_RTE_MACHINE = default" but no success.
>
> Is there anything that needs to be followed to overcome this blocking issue?
>
> Regards
> Vikram
You need to to set CONFIG_RTE_MACHINE to the minimum cpu type that your
product needs to run on. That value sets the compiler flags which determine
which extended CPU instructions will be used.
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [dpdk-users] Segmentation fault at rte_cpu_get_flag_enabled
2020-04-20 15:07 ` Stephen Hemminger
@ 2020-04-20 18:03 ` vikram T
2020-04-20 20:23 ` Stephen Hemminger
0 siblings, 1 reply; 4+ messages in thread
From: vikram T @ 2020-04-20 18:03 UTC (permalink / raw)
To: Stephen Hemminger; +Cc: users
Hi Stephen,
Thanks for the response.
As far as I know the value given to CONFIG_RTE_MACHINE may be any of these:
( supported in DPDK)
armv7a default dpaa2 ivb nhm power8 snb thunderx2
xgene1
armv8a dpaa hsw native octeontx2 silvermont thunderx wsm
How do I find/determine the minimum CPU type from the above supported
machines?
Additionally our product runs on multiple machines and hence would like to
select the most minimum CPU set to avoid this issue.
Regards
Vikram
On Mon, Apr 20, 2020 at 8:37 PM Stephen Hemminger <
stephen@networkplumber.org> wrote:
> On Mon, 20 Apr 2020 12:39:02 +0530
> vikram T <vikramet@gmail.com> wrote:
>
> > Hi,
> > I have been seeing the application crashes( DPDK v19.08) with
> segmentation
> > fault as below:
> > (gdb) bt
> > #0 0x000000000054fda9 in rte_cpu_get_flag_enabled ()
> > #1 0x00000000004f5d5e in rte_hash_crc_init_alg ()
> > #2 0x000000000084cf7d in __libc_csu_init ()
> > #3 0x00007ffff4df9425 in __libc_start_main () from /lib64/libc.so.6
> > #4 0x00000000005048df in _start ()
> > (gdb) q
> >
> > Here the DPDK is built and linked on the machine different from the
> target
> > machine.
> > Hence used the flag - "CONFIG_RTE_MACHINE = default" but no success.
> >
> > Is there anything that needs to be followed to overcome this blocking
> issue?
> >
> > Regards
> > Vikram
>
> You need to to set CONFIG_RTE_MACHINE to the minimum cpu type that your
> product needs to run on. That value sets the compiler flags which determine
> which extended CPU instructions will be used.
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [dpdk-users] Segmentation fault at rte_cpu_get_flag_enabled
2020-04-20 18:03 ` vikram T
@ 2020-04-20 20:23 ` Stephen Hemminger
0 siblings, 0 replies; 4+ messages in thread
From: Stephen Hemminger @ 2020-04-20 20:23 UTC (permalink / raw)
To: vikram T; +Cc: users
On Mon, 20 Apr 2020 23:33:56 +0530
vikram T <vikramet@gmail.com> wrote:
> Hi Stephen,
> Thanks for the response.
> As far as I know the value given to CONFIG_RTE_MACHINE may be any of these:
> ( supported in DPDK)
>
> armv7a default dpaa2 ivb nhm power8 snb thunderx2
> xgene1
> armv8a dpaa hsw native octeontx2 silvermont thunderx wsm
>
> How do I find/determine the minimum CPU type from the above supported
> machines?
> Additionally our product runs on multiple machines and hence would like to
> select the most minimum CPU set to avoid this issue.
> Regards
> Vikram
Are you on Intel (x86) or other platform?
The documentation there is referring to the default available config files.
The CONFIG_RTE_MACHINE values available, depend on the compiler and the architecture.
Depending on the platform core2 or nehalem might be good choices.
For GCC compiler and x86 architecture this is on the gcc man page.
x86 Options
These -m options are defined for the x86 family of computers.
-march=cpu-type
Generate instructions for the machine type cpu-type. In contrast to -mtune=cpu-type, which merely tunes the
generated code for the specified cpu-type, -march=cpu-type allows GCC to generate code that may not run at
all on processors other than the one indicated. Specifying -march=cpu-type implies -mtune=cpu-type.
The choices for cpu-type are:
native
This selects the CPU to generate code for at compilation time by determining the processor type of the
compiling machine. Using -march=native enables all instruction subsets supported by the local machine
(hence the result might not run on different machines). Using -mtune=native produces code optimized for
the local machine under the constraints of the selected instruction set.
i386
Original Intel i386 CPU.
i486
Intel i486 CPU. (No scheduling is implemented for this chip.)
i586
pentium
Intel Pentium CPU with no MMX support.
lakemont
Intel Lakemont MCU, based on Intel Pentium CPU.
pentium-mmx
Intel Pentium MMX CPU, based on Pentium core with MMX instruction set support.
pentiumpro
Intel Pentium Pro CPU.
i686
When used with -march, the Pentium Pro instruction set is used, so the code runs on all i686 family
chips. When used with -mtune, it has the same meaning as generic.
pentium2
Intel Pentium II CPU, based on Pentium Pro core with MMX instruction set support.
pentium3
pentium3m
Intel Pentium III CPU, based on Pentium Pro core with MMX and SSE instruction set support.
pentium-m
Intel Pentium M; low-power version of Intel Pentium III CPU with MMX, SSE and SSE2 instruction set
support. Used by Centrino notebooks.
pentium4
pentium4m
Intel Pentium 4 CPU with MMX, SSE and SSE2 instruction set support.
prescott
Improved version of Intel Pentium 4 CPU with MMX, SSE, SSE2 and SSE3 instruction set support.
nocona
Improved version of Intel Pentium 4 CPU with 64-bit extensions, MMX, SSE, SSE2 and SSE3 instruction set
support.
core2
Intel Core 2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support.
nehalem
Intel Nehalem CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and POPCNT
instruction set support.
westmere
Intel Westmere CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES and
PCLMUL instruction set support.
sandybridge
Intel Sandy Bridge CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX,
AES and PCLMUL instruction set support.
ivybridge
Intel Ivy Bridge CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX,
AES, PCLMUL, FSGSBASE, RDRND and F16C instruction set support.
haswell
Intel Haswell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT,
AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2 and F16C instruction set support.
broadwell
Intel Broadwell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT,
AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX and PREFETCHW instruction set
support.
skylake
Intel Skylake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT,
AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT,
XSAVEC and XSAVES instruction set support.
bonnell
Intel Bonnell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support.
silvermont
Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT,
AES, PCLMUL and RDRND instruction set support.
knl Intel Knight's Landing CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2,
POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, AVX512F,
AVX512PF, AVX512ER and AVX512CD instruction set support.
skylake-avx512
Intel Skylake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2,
POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW,
CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ and AVX512CD instruction set support.
k6 AMD K6 CPU with MMX instruction set support.
k6-2
k6-3
Improved versions of AMD K6 CPU with MMX and 3DNow! instruction set support.
athlon
athlon-tbird
AMD Athlon CPU with MMX, 3dNOW!, enhanced 3DNow! and SSE prefetch instructions support.
athlon-4
athlon-xp
athlon-mp
Improved AMD Athlon CPU with MMX, 3DNow!, enhanced 3DNow! and full SSE instruction set support.
k8
opteron
athlon64
athlon-fx
Processors based on the AMD K8 core with x86-64 instruction set support, including the AMD Opteron,
Athlon 64, and Athlon 64 FX processors. (This supersets MMX, SSE, SSE2, 3DNow!, enhanced 3DNow! and
64-bit instruction set extensions.)
k8-sse3
opteron-sse3
athlon64-sse3
Improved versions of AMD K8 cores with SSE3 instruction set support.
amdfam10
barcelona
CPUs based on AMD Family 10h cores with x86-64 instruction set support. (This supersets MMX, SSE, SSE2,
SSE3, SSE4A, 3DNow!, enhanced 3DNow!, ABM and 64-bit instruction set extensions.)
bdver1
CPUs based on AMD Family 15h cores with x86-64 instruction set support. (This supersets FMA4, AVX, XOP,
LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction
set extensions.)
bdver2
AMD Family 15h core based CPUs with x86-64 instruction set support. (This supersets BMI, TBM, F16C, FMA,
FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and
64-bit instruction set extensions.)
bdver3
AMD Family 15h core based CPUs with x86-64 instruction set support. (This supersets BMI, TBM, F16C, FMA,
FMA4, FSGSBASE, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2,
ABM and 64-bit instruction set extensions.
bdver4
AMD Family 15h core based CPUs with x86-64 instruction set support. (This supersets BMI, BMI2, TBM,
F16C, FMA, FMA4, FSGSBASE, AVX, AVX2, XOP, LWP, AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A,
SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.
znver1
AMD Family 17h core based CPUs with x86-64 instruction set support. (This supersets BMI, BMI2, F16C,
FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, MWAITX, SHA, CLZERO, AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2,
SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, and 64-bit instruction set
extensions.
btver1
CPUs based on AMD Family 14h cores with x86-64 instruction set support. (This supersets MMX, SSE, SSE2,
SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit instruction set extensions.)
btver2
CPUs based on AMD Family 16h cores with x86-64 instruction set support. This includes MOVBE, F16C, BMI,
AVX, PCL_MUL, AES, SSE4.2, SSE4.1, CX16, ABM, SSE4A, SSSE3, SSE3, SSE2, SSE, MMX and 64-bit instruction
set extensions.
winchip-c6
IDT WinChip C6 CPU, dealt in same way as i486 with additional MMX instruction set support.
winchip2
IDT WinChip 2 CPU, dealt in same way as i486 with additional MMX and 3DNow! instruction set support.
c3 VIA C3 CPU with MMX and 3DNow! instruction set support. (No scheduling is implemented for this chip.)
c3-2
VIA C3-2 (Nehemiah/C5XL) CPU with MMX and SSE instruction set support. (No scheduling is implemented for
this chip.)
c7 VIA C7 (Esther) CPU with MMX, SSE, SSE2 and SSE3 instruction set support. (No scheduling is implemented
for this chip.)
samuel-2
VIA Eden Samuel 2 CPU with MMX and 3DNow! instruction set support. (No scheduling is implemented for
this chip.)
nehemiah
VIA Eden Nehemiah CPU with MMX and SSE instruction set support. (No scheduling is implemented for this
chip.)
esther
VIA Eden Esther CPU with MMX, SSE, SSE2 and SSE3 instruction set support. (No scheduling is implemented
for this chip.)
eden-x2
VIA Eden X2 CPU with x86-64, MMX, SSE, SSE2 and SSE3 instruction set support. (No scheduling is
implemented for this chip.)
eden-x4
VIA Eden X4 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 instruction set
support. (No scheduling is implemented for this chip.)
nano
Generic VIA Nano CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support. (No scheduling
is implemented for this chip.)
nano-1000
VIA Nano 1xxx CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support. (No scheduling is
implemented for this chip.)
nano-2000
VIA Nano 2xxx CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support. (No scheduling is
implemented for this chip.)
nano-3000
VIA Nano 3xxx CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 instruction set support. (No
scheduling is implemented for this chip.)
nano-x2
VIA Nano Dual Core CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 instruction set support. (No
scheduling is implemented for this chip.)
nano-x4
VIA Nano Quad Core CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 instruction set support. (No
scheduling is implemented for this chip.)
geode
AMD Geode embedded processor with MMX and 3DNow! instruction set support.
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-04-20 20:24 UTC | newest]
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2020-04-20 7:09 [dpdk-users] Segmentation fault at rte_cpu_get_flag_enabled vikram T
2020-04-20 15:07 ` Stephen Hemminger
2020-04-20 18:03 ` vikram T
2020-04-20 20:23 ` Stephen Hemminger
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