============================================================================================================================================================= || Counter Name || Counter Value ||| Performance Analysis || Analysis Value [Units] || ============================================================================================================================================================= || Level 0 MTT Cache Hit || 0 ||| Bandwidth || || Level 0 MTT Cache Miss || 0 ||--------------------------------------------------------------------------- || Level 1 MTT Cache Hit || 0 ||| RX BandWidth || 55.039 [Gb/s] || || Level 1 MTT Cache Miss || 0 ||| TX BandWidth || 0 [Gb/s] || || Level 0 MPT Cache Hit || 0 ||=========================================================================== || Level 0 MPT Cache Miss || 0 ||| Memory || || Level 1 MPT Cache Hit || 0 ||--------------------------------------------------------------------------- || Level 1 MPT Cache Miss || 0 ||| RX Indirect Memory Keys Rate || 0 [Keys/Packet] || || Indirect Memory Key Access || 0 ||=========================================================================== || ICM Cache Miss || 38 ||| PCIe Bandwidth || || PCIe Internal Back Pressure || 0 ||--------------------------------------------------------------------------- || Outbound Stalled Reads || 0 ||| PCIe Inbound Available BW || 251.3851 [Gb/s] || || Outbound Stalled Writes || 0 ||| PCIe Inbound BW Utilization || 0.0027 [%] || || PCIe Read Stalled due to No Read Engines || 0 ||| PCIe Inbound Used BW || 0.0069 [Gb/s] || || PCIe Read Stalled due to No Completion Buffer || 0 ||| PCIe Outbound Available BW || 251.3851 [Gb/s] || || PCIe Read Stalled due to Ordering || 0 ||| PCIe Outbound BW Utilization || 0.0025 [%] || || RX IPsec Packets || 0 ||| PCIe Outbound Used BW || 0.0062 [Gb/s] || || Back Pressure from RXD to PSA || 0 ||=========================================================================== || Chip Frequency || 429.9925 ||| PCIe Latency || || Back Pressure from RXB Buffer to RXB FIFO || 0 ||--------------------------------------------------------------------------- || Back Pressure from PSA switch to RXT || 0 ||| PCIe Avg Latency || 523 [NS] || || Back Pressure from PSA switch to RXB || 0 ||| PCIe Max Latency || 548 [NS] || || Back Pressure from PSA switch to RXD || 0 ||| PCIe Min Latency || 511 [NS] || || Back Pressure from Internal MMU to RX Descriptor Handling || 107,498,115 ||=========================================================================== || Receive WQE Cache Hit || 0 ||| PCIe Unit Internal Latency || || Receive WQE Cache Miss || 0 ||--------------------------------------------------------------------------- || Back Pressure from PCIe to Packet Scatter || 0 ||| PCIe Internal Avg Latency || 4 [NS] || || RX Steering Packets || 107,498,116 ||| PCIe Internal Max Latency || 4 [NS] || || RX Steering Packets Fast Path || 0 ||| PCIe Internal Min Latency || 4 [NS] || || EQ All State Machines Busy || 0 ||=========================================================================== || CQ All State Machines Busy || 0 ||| Packet Rate || || MSI-X All State Machines Busy || 0 ||--------------------------------------------------------------------------- || CQE Compression Sessions || 0 ||| RX Packet Rate || 107,498,115 [Packets/Seconds] || || Compressed CQEs || 0 ||| TX Packet Rate || 0 [Packets/Seconds] || || Compression Session Closed due to EQE || 0 ||=========================================================================== || Compression Session Closed due to Timeout || 0 ||| eSwitch || || Compression Session Closed due to Mismatch || 0 ||--------------------------------------------------------------------------- || Compression Session Closed due to PCIe Idle || 0 ||| RX Hops Per Packet || 4.5503 [Hops/Packet] || || Compression Session Closed due to S2CQE || 0 ||| RX Optimal Hops Per Packet Per Pipe || 2.2751 [Hops/Packet] || || Compressed CQE Strides || 0 ||| RX Optimal Packet Rate Bottleneck || 188.9994 [MPPS] || || Compression Session Closed due to LRO || 0 ||| RX Packet Rate Bottleneck || 182.5796 [MPPS] || || TX Descriptor Handling Stopped due to Limited State || 0 ||| TX Hops Per Packet || 0 [Hops/Packet] || || TX Descriptor Handling Stopped due to Limited VL || 0 ||| TX Optimal Hops Per Packet Per Pipe || 0 [Hops/Packet] || || TX Descriptor Handling Stopped due to De-schedule || 0 ||| TX Optimal Packet Rate Bottleneck || 0 [MPPS] || || TX Descriptor Handling Stopped due to Work Done || 0 ||| TX Packet Rate Bottleneck || 0 [MPPS] || || TX Descriptor Handling Stopped due to E2E Credits || 0 ||=========================================================================== || Line Transmitted Port 1 || 0 || || Line Transmitted Port 2 || 0 || || Line Transmitted Loop Back || 0 || || RX_PSA0 Steering Pipe 0 || 253,168,409 || || RX_PSA0 Steering Pipe 1 || 235,977,321 || || RX_PSA0 Steering Cache Access Pipe 0 || 224,400,319 || || RX_PSA0 Steering Cache Access Pipe 1 || 208,687,547 || || RX_PSA0 Steering Cache Hit Pipe 0 || 224,400,319 || || RX_PSA0 Steering Cache Hit Pipe 1 || 208,687,547 || || RX_PSA0 Steering Cache Miss Pipe 0 || 0 || || RX_PSA0 Steering Cache Miss Pipe 1 || 0 || || RX_PSA1 Steering Pipe 0 || 253,168,409 || || RX_PSA1 Steering Pipe 1 || 235,977,321 || || RX_PSA1 Steering Cache Access Pipe 0 || 224,400,319 || || RX_PSA1 Steering Cache Access Pipe 1 || 208,687,547 || || RX_PSA1 Steering Cache Hit Pipe 0 || 224,400,319 || || RX_PSA1 Steering Cache Hit Pipe 1 || 208,687,547 || || RX_PSA1 Steering Cache Miss Pipe 0 || 0 || || RX_PSA1 Steering Cache Miss Pipe 1 || 0 || || TX_PSA0 Steering Pipe 0 || 0 || || TX_PSA0 Steering Pipe 1 || 0 || || TX_PSA0 Steering Cache Access Pipe 0 || 0 || || TX_PSA0 Steering Cache Access Pipe 1 || 0 || || TX_PSA0 Steering Cache Hit Pipe 0 || 0 || || TX_PSA0 Steering Cache Hit Pipe 1 || 0 || || TX_PSA0 Steering Cache Miss Pipe 0 || 0 || || TX_PSA0 Steering Cache Miss Pipe 1 || 0 || || TX_PSA1 Steering Pipe 0 || 0 || || TX_PSA1 Steering Pipe 1 || 0 || || TX_PSA1 Steering Cache Access Pipe 0 || 0 || || TX_PSA1 Steering Cache Access Pipe 1 || 0 || || TX_PSA1 Steering Cache Hit Pipe 0 || 0 || || TX_PSA1 Steering Cache Hit Pipe 1 || 0 || || TX_PSA1 Steering Cache Miss Pipe 0 || 0 || || TX_PSA1 Steering Cache Miss Pipe 1 || 0 || ==================================================================================