============================================================================================================================================================= || Counter Name || Counter Value ||| Performance Analysis || Analysis Value [Units] || ============================================================================================================================================================= || Level 0 MTT Cache Hit || 150,044,655 ||| Bandwidth || || Level 0 MTT Cache Miss || 5,878,330 ||--------------------------------------------------------------------------- || Level 1 MTT Cache Hit || 0 ||| RX BandWidth || 76.1929 [Gb/s] || || Level 1 MTT Cache Miss || 0 ||| TX BandWidth || 0 [Gb/s] || || Level 0 MPT Cache Hit || 157,018,528 ||=========================================================================== || Level 0 MPT Cache Miss || 151,533 ||| Memory || || Level 1 MPT Cache Hit || 0 ||--------------------------------------------------------------------------- || Level 1 MPT Cache Miss || 0 ||| RX Indirect Memory Keys Rate || 0 [Keys/Packet] || || Indirect Memory Key Access || 0 ||=========================================================================== || ICM Cache Miss || 49 ||| PCIe Bandwidth || || PCIe Internal Back Pressure || 1 ||--------------------------------------------------------------------------- || Outbound Stalled Reads || 0 ||| PCIe Inbound Available BW || 251.3869 [Gb/s] || || Outbound Stalled Writes || 0 ||| PCIe Inbound BW Utilization || 13.15 [%] || || PCIe Read Stalled due to No Read Engines || 0 ||| PCIe Inbound Used BW || 33.0575 [Gb/s] || || PCIe Read Stalled due to No Completion Buffer || 0 ||| PCIe Outbound Available BW || 251.3869 [Gb/s] || || PCIe Read Stalled due to Ordering || 0 ||| PCIe Outbound BW Utilization || 46.5101 [%] || || RX IPsec Packets || 0 ||| PCIe Outbound Used BW || 116.9203 [Gb/s] || || Back Pressure from RXD to PSA || 0 ||=========================================================================== || Chip Frequency || 429.994 ||| PCIe Latency || || Back Pressure from RXB Buffer to RXB FIFO || 0 ||--------------------------------------------------------------------------- || Back Pressure from PSA switch to RXT || 0 ||| PCIe Avg Latency || 512 [NS] || || Back Pressure from PSA switch to RXB || 0 ||| PCIe Max Latency || 1,127 [NS] || || Back Pressure from PSA switch to RXD || 0 ||| PCIe Min Latency || 409 [NS] || || Back Pressure from Internal MMU to RX Descriptor Handling || 150,595,604 ||=========================================================================== || Receive WQE Cache Hit || 147,113,254 ||| PCIe Unit Internal Latency || || Receive WQE Cache Miss || 1,701,085 ||--------------------------------------------------------------------------- || Back Pressure from PCIe to Packet Scatter || 1,796,240 ||| PCIe Internal Avg Latency || 4 [NS] || || RX Steering Packets || 148,814,339 ||| PCIe Internal Max Latency || 4 [NS] || || RX Steering Packets Fast Path || 0 ||| PCIe Internal Min Latency || 4 [NS] || || EQ All State Machines Busy || 0 ||=========================================================================== || CQ All State Machines Busy || 0 ||| Packet Rate || || MSI-X All State Machines Busy || 0 ||--------------------------------------------------------------------------- || CQE Compression Sessions || 127,741,993 ||| RX Packet Rate || 148,814,339 [Packets/Seconds] || || Compressed CQEs || 18,529,127 ||| TX Packet Rate || 0 [Packets/Seconds] || || Compression Session Closed due to EQE || 0 ||=========================================================================== || Compression Session Closed due to Timeout || 0 ||| eSwitch || || Compression Session Closed due to Mismatch || 0 ||--------------------------------------------------------------------------- || Compression Session Closed due to PCIe Idle || 0 ||| RX Hops Per Packet || 3.5787 [Hops/Packet] || || Compression Session Closed due to S2CQE || 0 ||| RX Optimal Hops Per Packet Per Pipe || 1.7894 [Hops/Packet] || || Compressed CQE Strides || 0 ||| RX Optimal Packet Rate Bottleneck || 240.3007 [MPPS] || || Compression Session Closed due to LRO || 0 ||| RX Packet Rate Bottleneck || 235.3318 [MPPS] || || TX Descriptor Handling Stopped due to Limited State || 0 ||| TX Hops Per Packet || 0 [Hops/Packet] || || TX Descriptor Handling Stopped due to Limited VL || 0 ||| TX Optimal Hops Per Packet Per Pipe || 0 [Hops/Packet] || || TX Descriptor Handling Stopped due to De-schedule || 0 ||| TX Optimal Packet Rate Bottleneck || 0 [MPPS] || || TX Descriptor Handling Stopped due to Work Done || 0 ||| TX Packet Rate Bottleneck || 0 [MPPS] || || TX Descriptor Handling Stopped due to E2E Credits || 0 ||=========================================================================== || Line Transmitted Port 1 || 0 || || Line Transmitted Port 2 || 0 || || Line Transmitted Loop Back || 0 || || RX_PSA0 Steering Pipe 0 || 271,910,888 || || RX_PSA0 Steering Pipe 1 || 260,654,182 || || RX_PSA0 Steering Cache Access Pipe 0 || 233,741,717 || || RX_PSA0 Steering Cache Access Pipe 1 || 224,534,200 || || RX_PSA0 Steering Cache Hit Pipe 0 || 233,741,717 || || RX_PSA0 Steering Cache Hit Pipe 1 || 224,534,200 || || RX_PSA0 Steering Cache Miss Pipe 0 || 0 || || RX_PSA0 Steering Cache Miss Pipe 1 || 0 || || RX_PSA1 Steering Pipe 0 || 271,910,888 || || RX_PSA1 Steering Pipe 1 || 260,654,182 || || RX_PSA1 Steering Cache Access Pipe 0 || 233,741,717 || || RX_PSA1 Steering Cache Access Pipe 1 || 224,534,200 || || RX_PSA1 Steering Cache Hit Pipe 0 || 233,741,717 || || RX_PSA1 Steering Cache Hit Pipe 1 || 224,534,200 || || RX_PSA1 Steering Cache Miss Pipe 0 || 0 || || RX_PSA1 Steering Cache Miss Pipe 1 || 0 || || TX_PSA0 Steering Pipe 0 || 0 || || TX_PSA0 Steering Pipe 1 || 0 || || TX_PSA0 Steering Cache Access Pipe 0 || 0 || || TX_PSA0 Steering Cache Access Pipe 1 || 0 || || TX_PSA0 Steering Cache Hit Pipe 0 || 0 || || TX_PSA0 Steering Cache Hit Pipe 1 || 0 || || TX_PSA0 Steering Cache Miss Pipe 0 || 0 || || TX_PSA0 Steering Cache Miss Pipe 1 || 0 || || TX_PSA1 Steering Pipe 0 || 0 || || TX_PSA1 Steering Pipe 1 || 0 || || TX_PSA1 Steering Cache Access Pipe 0 || 0 || || TX_PSA1 Steering Cache Access Pipe 1 || 0 || || TX_PSA1 Steering Cache Hit Pipe 0 || 0 || || TX_PSA1 Steering Cache Hit Pipe 1 || 0 || || TX_PSA1 Steering Cache Miss Pipe 0 || 0 || || TX_PSA1 Steering Cache Miss Pipe 1 || 0 || ==================================================================================