* Intel E810 and X710 NIC DMA control
@ 2025-05-01 19:36 Lombardo, Ed
2025-05-01 20:29 ` Stephen Hemminger
0 siblings, 1 reply; 2+ messages in thread
From: Lombardo, Ed @ 2025-05-01 19:36 UTC (permalink / raw)
To: users
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Hi,
I want control the Intel NICs (E810 and X710) DMA to either the hugepage memory on socket 0 or socket 1. Is there a way to do this in DPDK 24.11?
I have created two mempools, one on socket 0 and one on socket 1. Now when packets arrive at the NIC receive ports (1 and 2) I only see mbufs in mempool on the CPU socket where the NIC is located being used to .
Thanks,
Ed
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* Re: Intel E810 and X710 NIC DMA control
2025-05-01 19:36 Intel E810 and X710 NIC DMA control Lombardo, Ed
@ 2025-05-01 20:29 ` Stephen Hemminger
0 siblings, 0 replies; 2+ messages in thread
From: Stephen Hemminger @ 2025-05-01 20:29 UTC (permalink / raw)
To: users
On Thu, 1 May 2025 19:36:54 +0000
"Lombardo, Ed" <Ed.Lombardo@netscout.com> wrote:
> Hi,
> I want control the Intel NICs (E810 and X710) DMA to either the hugepage memory on socket 0 or socket 1. Is there a way to do this in DPDK 24.11?
>
> I have created two mempools, one on socket 0 and one on socket 1. Now when packets arrive at the NIC receive ports (1 and 2) I only see mbufs in mempool on the CPU socket where the NIC is located being used to .
>
> Thanks,
> Ed
The NIC will use the mempool you pass during configuration in
rte_eth_rx_queue_setup()
You can also get more detailed with rx segment splitting.
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