From: Antonio Di Bacco <a.dibacco.ks@gmail.com>
To: users@dpdk.org
Subject: DPDK performances surprise
Date: Wed, 18 May 2022 18:40:37 +0200 [thread overview]
Message-ID: <CAO8pfFnSf070rr3n5LXwY9cSB0jFYF_3ENmVRH8q_AaBBKoJ=w@mail.gmail.com> (raw)
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I recently read a performance test where l2fwd was able to receive packets
(8000B) from a 100 Gbps card, swap the L2 addresses and send them back to
the same port to be received by an ethernet analyzer. The throughput
achieved was close to 100 Gbps on a XEON machine (Intel(R) Xeon(R) Platinum
8176 CPU @ 2.10GHz) . This is the same processor I have and I know that, if
I try to write around 8000B to the attached DDR4 (2666MT/s) on an allocated
1GB hugepage, I get a maximum throughput of around 20GB/s.
Now, a 100 Gbps can generate a flow of around 12 GB/s, these packets have
to be written to the DDR and then read back to swap L2 addresses and this
leads to a cumulative bandwidth on the DDR that is around 2x12 GB/s and is
more than the 20GB/s of available bandwidth on the DDR4.
How can this be possible ?
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next reply other threads:[~2022-05-18 16:40 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-18 16:40 Antonio Di Bacco [this message]
2022-05-18 16:53 ` Sanford, Robert
2022-05-18 17:04 ` Stephen Hemminger
2022-05-19 9:03 ` Antonio Di Bacco
2022-05-19 8:29 ` Kinsella, Ray
2022-05-19 9:04 ` Antonio Di Bacco
2022-05-19 9:07 ` Kinsella, Ray
2022-05-19 15:05 ` Stephen Hemminger
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