* Intel E810 and X710 NIC DMA control
@ 2025-05-01 19:36 Lombardo, Ed
2025-05-01 20:29 ` Stephen Hemminger
0 siblings, 1 reply; 3+ messages in thread
From: Lombardo, Ed @ 2025-05-01 19:36 UTC (permalink / raw)
To: users
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Hi,
I want control the Intel NICs (E810 and X710) DMA to either the hugepage memory on socket 0 or socket 1. Is there a way to do this in DPDK 24.11?
I have created two mempools, one on socket 0 and one on socket 1. Now when packets arrive at the NIC receive ports (1 and 2) I only see mbufs in mempool on the CPU socket where the NIC is located being used to .
Thanks,
Ed
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: Intel E810 and X710 NIC DMA control
2025-05-01 19:36 Intel E810 and X710 NIC DMA control Lombardo, Ed
@ 2025-05-01 20:29 ` Stephen Hemminger
2025-05-06 21:45 ` Lombardo, Ed
0 siblings, 1 reply; 3+ messages in thread
From: Stephen Hemminger @ 2025-05-01 20:29 UTC (permalink / raw)
To: users
On Thu, 1 May 2025 19:36:54 +0000
"Lombardo, Ed" <Ed.Lombardo@netscout.com> wrote:
> Hi,
> I want control the Intel NICs (E810 and X710) DMA to either the hugepage memory on socket 0 or socket 1. Is there a way to do this in DPDK 24.11?
>
> I have created two mempools, one on socket 0 and one on socket 1. Now when packets arrive at the NIC receive ports (1 and 2) I only see mbufs in mempool on the CPU socket where the NIC is located being used to .
>
> Thanks,
> Ed
The NIC will use the mempool you pass during configuration in
rte_eth_rx_queue_setup()
You can also get more detailed with rx segment splitting.
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: Intel E810 and X710 NIC DMA control
2025-05-01 20:29 ` Stephen Hemminger
@ 2025-05-06 21:45 ` Lombardo, Ed
0 siblings, 0 replies; 3+ messages in thread
From: Lombardo, Ed @ 2025-05-06 21:45 UTC (permalink / raw)
To: Stephen Hemminger, users
Hi Stephen,
Thanks, I will try your suggestion, appreciate your help.
Regards,
Ed
-----Original Message-----
From: Stephen Hemminger <stephen@networkplumber.org>
Sent: Thursday, May 1, 2025 4:29 PM
To: users@dpdk.org
Subject: Re: Intel E810 and X710 NIC DMA control
External Email: This message originated outside of NETSCOUT. Do not click links or open attachments unless you recognize the sender and know the content is safe.
On Thu, 1 May 2025 19:36:54 +0000
"Lombardo, Ed" <Ed.Lombardo@netscout.com> wrote:
> Hi,
> I want control the Intel NICs (E810 and X710) DMA to either the hugepage memory on socket 0 or socket 1. Is there a way to do this in DPDK 24.11?
>
> I have created two mempools, one on socket 0 and one on socket 1. Now when packets arrive at the NIC receive ports (1 and 2) I only see mbufs in mempool on the CPU socket where the NIC is located being used to .
>
> Thanks,
> Ed
The NIC will use the mempool you pass during configuration in
rte_eth_rx_queue_setup()
You can also get more detailed with rx segment splitting.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2025-05-01 19:36 Intel E810 and X710 NIC DMA control Lombardo, Ed
2025-05-01 20:29 ` Stephen Hemminger
2025-05-06 21:45 ` Lombardo, Ed
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