From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 44886A05D3 for ; Tue, 26 Mar 2019 11:53:54 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 31C4A2BFA; Tue, 26 Mar 2019 11:53:53 +0100 (CET) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id 484B82BD3 for ; Tue, 26 Mar 2019 11:53:51 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Mar 2019 03:53:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,271,1549958400"; d="scan'208";a="155883248" Received: from irsmsx101.ger.corp.intel.com ([163.33.3.153]) by fmsmga004.fm.intel.com with ESMTP; 26 Mar 2019 03:53:49 -0700 Received: from irsmsx102.ger.corp.intel.com ([169.254.2.146]) by IRSMSX101.ger.corp.intel.com ([169.254.1.230]) with mapi id 14.03.0415.000; Tue, 26 Mar 2019 10:53:48 +0000 From: "Van Haaren, Harry" To: Dell Will , users Thread-Topic: Why not prefetch the second cache line of struct rte_mbuf for better performance ? Thread-Index: AQHU47LRM/ZH6IaskkW9FTl23HVx5KYdu5CQ Date: Tue, 26 Mar 2019 10:53:48 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMjQ1Y2FjZDktOTgxZS00NzRiLWEwMTgtNGFmZmMyNzZjMjAwIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiMVVHWm1rcjNlcFdTNjc1bUJSa2ZmMkw2ZlM1aE5yYVdxWStOOFFHSnluZ3JqQVMxaEUxZldhVzlMZno2WEJkXC8ifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [163.33.239.181] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-users] Why not prefetch the second cache line of struct rte_mbuf for better performance ? X-BeenThere: users@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK usage discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: users-bounces@dpdk.org Sender: "users" > -----Original Message----- > From: users [mailto:users-bounces@dpdk.org] On Behalf Of Dell Will > Sent: Tuesday, March 26, 2019 9:04 AM > To: users > Subject: [dpdk-users] Why not prefetch the second cache line of struct > rte_mbuf for better performance ? >=20 > Hello, everybody Hi, > I find that many codes in DPDK only prefetch the first cache line of stru= ct > rte_mbuf. > The struct rte_mbuf has 2 cache lines. > Why not prefetch the second line ? A reason that cache-line 2 is not always prefetched is that it is not always going to be used. For example, the packet RX routines modify only the 1-st cache line, and do not require the 2nd to be available. > Is it hinted that the CPU (x64 or ARM) always automatically prefetch the > next immediately followed cache line ? Some details on x86-64 prefetchers here, particularly the "Adjacent Cache-L= ine Prefetch" is of interest; https://software.intel.com/en-us/articles/optimizing-application-performanc= e-on-intel-coret-microarchitecture-using-hardware-implemented-prefetchers [Side note, x64 is actually a different architecture than x86-64]. > Thanks a lot ! Hope that helps, -Harry