From: "Phil Yang (Arm Technology China)" <Phil.Yang@arm.com>
To: "jgrajcia@cisco.com" <jgrajcia@cisco.com>,
"users@dpdk.org" <users@dpdk.org>
Cc: "damarion@cisco.com" <damarion@cisco.com>,
Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>,
"Gavin Hu (Arm Technology China)" <Gavin.Hu@arm.com>,
nd <nd@arm.com>
Subject: [dpdk-users] Consulting the usage of rte_mb in memif rx/tx path
Date: Fri, 2 Aug 2019 11:09:03 +0000 [thread overview]
Message-ID: <VE1PR08MB4640A88326C05104D69A1935E9D90@VE1PR08MB4640.eurprd08.prod.outlook.com> (raw)
Hi Jakub,
I am trying to understand the rte_mb() in eth_memif_rx/tx functions. What's the purpose of this barrier?
https://github.com/DPDK/dpdk/blob/master/drivers/net/memif/rte_eth_memif.c
In my understanding, the RX and TX processes are handling in the same core (e.g the testpmd forwarding engine) on each side (Master/Salve).
x86 platform guarantees that all stores are visible in program order and load-load are also in program order. And it has data dependence between the before-rte_mb and the after-rte_mb operation (update ring->head/tail). So why do we need this barrier?
BTW, on Aarch64, the rte_mb() is a 'DSB SY', which will stop the pipeline. So after removed this barrier, the testpmd with memif vPMD got 3.5% performance improvement.
Best Regards,
Phil Yang
reply other threads:[~2019-08-02 11:09 UTC|newest]
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