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charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Subject: [dpdk-users] Consulting the usage of rte_mb in memif rx/tx path X-BeenThere: users@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK usage discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: users-bounces@dpdk.org Sender: "users" Hi Jakub, I am trying to understand the rte_mb() in eth_memif_rx/tx functions. What's= the purpose of this barrier? https://github.com/DPDK/dpdk/blob/master/drivers/net/memif/rte_eth_memif.c In my understanding, the RX and TX processes are handling in the same core = (e.g the testpmd forwarding engine) on each side (Master/Salve). x86 platform guarantees that all stores are visible in program order and lo= ad-load are also in program order. And it has data dependence between the b= efore-rte_mb and the after-rte_mb operation (update ring->head/tail). So wh= y do we need this barrier? BTW, on Aarch64, the rte_mb() is a 'DSB SY', which will stop the pipeline. = So after removed this barrier, the testpmd with memif vPMD got 3.5% perform= ance improvement. Best Regards, Phil Yang