From: Andrey Vesnovaty <andreyv@nvidia.com>
To: dev@dpdk.org
Cc: jer@marvell.com, jerinjacobk@gmail.com, thomas@monjalon.net,
ferruh.yigit@intel.com, stephen@networkplumber.org,
bruce.richardson@intel.com, orika@nvidia.com,
viacheslavo@nvidia.com, andrey.vesnovaty@gmail.com,
mdr@ashroe.eu, nhorman@tuxdriver.com, ajit.khaparde@broadcom.com,
samik.gupta@broadcom.com, Andrey Vesnovaty <andreyv@mellanox.com>,
Matan Azrad <matan@nvidia.com>,
Shahaf Shuler <shahafs@nvidia.com>
Subject: [dpdk-dev] [PATCH 1/4] common/mlx5: modify advanced Rx object via DevX
Date: Thu, 8 Oct 2020 15:18:44 +0300 [thread overview]
Message-ID: <20201008121848.15330-2-andreyv@nvidia.com> (raw)
In-Reply-To: <20201008121848.15330-1-andreyv@nvidia.com>
From: Andrey Vesnovaty <andreyv@mellanox.com>
Implement mlx5_devx_cmd_modify_tir() to modify TIR object using DevX
API.
Add related structs in mlx5_prm.h.
Signed-off-by: Andrey Vesnovaty <andreyv@mellanox.com>
---
drivers/common/mlx5/mlx5_devx_cmds.c | 84 +++++++++++++++++++
drivers/common/mlx5/mlx5_devx_cmds.h | 10 +++
drivers/common/mlx5/mlx5_prm.h | 29 +++++++
.../common/mlx5/rte_common_mlx5_version.map | 1 +
4 files changed, 124 insertions(+)
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index 7c81ae15a9..2b109c4f65 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -1080,6 +1080,90 @@ mlx5_devx_cmd_create_tir(void *ctx,
return tir;
}
+/**
+ * Modify TIR using DevX API.
+ *
+ * @param[in] tir
+ * Pointer to TIR DevX object structure.
+ * @param [in] modify_tir_attr
+ * Pointer to TIR modification attributes structure.
+ *
+ * @return
+ * 0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
+ struct mlx5_devx_modify_tir_attr *modify_tir_attr)
+{
+ struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;
+ uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};
+ uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
+ void *tir_ctx;
+ int ret;
+
+ MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
+ MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);
+ MLX5_SET64(modify_tir_in, in, modify_bitmask,
+ modify_tir_attr->modify_bitmask);
+
+ tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
+ if (modify_tir_attr->modify_bitmask &
+ MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {
+ MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
+ tir_attr->lro_timeout_period_usecs);
+ MLX5_SET(tirc, tir_ctx, lro_enable_mask,
+ tir_attr->lro_enable_mask);
+ MLX5_SET(tirc, tir_ctx, lro_max_msg_sz,
+ tir_attr->lro_max_msg_sz);
+ }
+ if (modify_tir_attr->modify_bitmask &
+ MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)
+ MLX5_SET(tirc, tir_ctx, indirect_table,
+ tir_attr->indirect_table);
+ if (modify_tir_attr->modify_bitmask &
+ MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {
+ int i;
+ void *outer, *inner;
+ MLX5_SET(tirc, tir_ctx, rx_hash_symmetric,
+ tir_attr->rx_hash_symmetric);
+ MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
+ for (i = 0; i < 10; i++) {
+ MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
+ tir_attr->rx_hash_toeplitz_key[i]);
+ }
+ outer = MLX5_ADDR_OF(tirc, tir_ctx,
+ rx_hash_field_selector_outer);
+ MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
+ tir_attr->rx_hash_field_selector_outer.l3_prot_type);
+ MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
+ tir_attr->rx_hash_field_selector_outer.l4_prot_type);
+ MLX5_SET
+ (rx_hash_field_select, outer, selected_fields,
+ tir_attr->rx_hash_field_selector_outer.selected_fields);
+ inner = MLX5_ADDR_OF(tirc, tir_ctx,
+ rx_hash_field_selector_inner);
+ MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
+ tir_attr->rx_hash_field_selector_inner.l3_prot_type);
+ MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
+ tir_attr->rx_hash_field_selector_inner.l4_prot_type);
+ MLX5_SET
+ (rx_hash_field_select, inner, selected_fields,
+ tir_attr->rx_hash_field_selector_inner.selected_fields);
+ }
+ if (modify_tir_attr->modify_bitmask &
+ MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {
+ MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
+ }
+ ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),
+ out, sizeof(out));
+ if (ret) {
+ DRV_LOG(ERR, "Failed to modify TIR using DevX");
+ rte_errno = errno;
+ return -errno;
+ }
+ return ret;
+}
+
/**
* Create RQT using DevX API.
*
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index 1c84cea851..ba6cb6ed51 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -190,6 +190,13 @@ struct mlx5_devx_tir_attr {
struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
};
+/* TIR attributes structure, used by TIR modify */
+struct mlx5_devx_modify_tir_attr {
+ uint32_t tirn:24;
+ uint64_t modify_bitmask;
+ struct mlx5_devx_tir_attr tir;
+};
+
/* RQT attributes structure, used by RQT operations. */
struct mlx5_devx_rqt_attr {
uint8_t rq_type;
@@ -434,6 +441,9 @@ __rte_internal
int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
struct mlx5_devx_rqt_attr *rqt_attr);
__rte_internal
+int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
+ struct mlx5_devx_modify_tir_attr *tir_attr);
+__rte_internal
int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
uint32_t ids[], uint32_t num);
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 20f2fccd4f..2dbae445b3 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -830,6 +830,7 @@ enum {
MLX5_CMD_OP_ACCESS_REGISTER = 0x805,
MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
MLX5_CMD_OP_CREATE_TIR = 0x900,
+ MLX5_CMD_OP_MODIFY_TIR = 0x901,
MLX5_CMD_OP_CREATE_SQ = 0X904,
MLX5_CMD_OP_MODIFY_SQ = 0X905,
MLX5_CMD_OP_CREATE_RQ = 0x908,
@@ -1858,6 +1859,34 @@ struct mlx5_ifc_create_tir_in_bits {
struct mlx5_ifc_tirc_bits ctx;
};
+enum {
+ MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO = 1ULL << 0,
+ MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE = 1ULL << 1,
+ MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH = 1ULL << 2,
+ /* bit 3 - tunneled_offload_en modify not supported */
+ MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN = 1ULL << 4,
+};
+
+struct mlx5_ifc_modify_tir_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x40];
+};
+
+struct mlx5_ifc_modify_tir_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x8];
+ u8 tirn[0x18];
+ u8 reserved_at_60[0x20];
+ u8 modify_bitmask[0x40];
+ u8 reserved_at_c0[0x40];
+ struct mlx5_ifc_tirc_bits ctx;
+};
+
enum {
MLX5_INLINE_Q_TYPE_RQ = 0x0,
MLX5_INLINE_Q_TYPE_VIRTQ = 0x1,
diff --git a/drivers/common/mlx5/rte_common_mlx5_version.map b/drivers/common/mlx5/rte_common_mlx5_version.map
index c4d57c08a7..884001ca7d 100644
--- a/drivers/common/mlx5/rte_common_mlx5_version.map
+++ b/drivers/common/mlx5/rte_common_mlx5_version.map
@@ -30,6 +30,7 @@ INTERNAL {
mlx5_devx_cmd_modify_rq;
mlx5_devx_cmd_modify_rqt;
mlx5_devx_cmd_modify_sq;
+ mlx5_devx_cmd_modify_tir;
mlx5_devx_cmd_modify_virtq;
mlx5_devx_cmd_qp_query_tis_td;
mlx5_devx_cmd_query_hca_attr;
--
2.26.2
next prev parent reply other threads:[~2020-10-08 12:19 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-08 12:18 [dpdk-dev] [PATCH 0/4] Shared action RSS PMD impl Andrey Vesnovaty
2020-10-08 12:18 ` Andrey Vesnovaty [this message]
2020-10-08 12:18 ` [dpdk-dev] [PATCH 2/4] net/mlx5: modify hash Rx queue objects Andrey Vesnovaty
2020-10-08 12:18 ` [dpdk-dev] [PATCH 3/4] net/mlx5: shared action PMD Andrey Vesnovaty
2020-10-08 12:18 ` [dpdk-dev] [PATCH 4/4] net/mlx5: driver support for shared action Andrey Vesnovaty
2020-10-23 10:24 ` [dpdk-dev] [PATCH v2 0/4] Shared action RSS PMD impl Andrey Vesnovaty
2020-10-23 10:24 ` [dpdk-dev] [PATCH v2 1/4] common/mlx5: modify advanced Rx object via DevX Andrey Vesnovaty
2020-10-23 14:16 ` Slava Ovsiienko
2020-10-23 10:24 ` [dpdk-dev] [PATCH v2 2/4] net/mlx5: modify hash Rx queue objects Andrey Vesnovaty
2020-10-23 14:17 ` Slava Ovsiienko
2020-10-23 10:24 ` [dpdk-dev] [PATCH v2 3/4] net/mlx5: shared action PMD Andrey Vesnovaty
2020-10-23 14:17 ` Slava Ovsiienko
2020-10-23 10:24 ` [dpdk-dev] [PATCH v2 4/4] net/mlx5: driver support for shared action Andrey Vesnovaty
2020-10-23 14:17 ` Slava Ovsiienko
2020-10-26 16:38 ` Ferruh Yigit
2020-10-26 16:40 ` Thomas Monjalon
2020-10-26 22:33 ` Asaf Penso
2020-10-26 16:40 ` Slava Ovsiienko
2020-10-25 12:43 ` [dpdk-dev] [PATCH v2 0/4] Shared action RSS PMD impl Raslan Darawsheh
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