* [dpdk-dev] [RFC 1/3] common/mlx5: add common qp_create
2021-08-18 15:14 [dpdk-dev] [RFC 0/3] mlx5: replaced hardware queue object Raja Zidane
@ 2021-08-18 15:14 ` Raja Zidane
2021-08-18 15:14 ` [dpdk-dev] [RFC 2/3] compress/mlx5: refactor queue creation in mlx5 add support to compress and regex drivers in BlueField3 Raja Zidane
2021-08-18 15:14 ` [dpdk-dev] [RFC 3/3] regex/mlx5: refactor queue creation in mlx5 add support to compress and regex drivers in Bluefield3 Raja Zidane
2 siblings, 0 replies; 4+ messages in thread
From: Raja Zidane @ 2021-08-18 15:14 UTC (permalink / raw)
To: dev; +Cc: matan, orika
Signed-off-by: Raja Zidane <rzidane@nvidia.com>
---
drivers/common/mlx5/mlx5_common_devx.c | 111 +++++++++++++++++++++++++
drivers/common/mlx5/mlx5_common_devx.h | 20 +++++
drivers/common/mlx5/version.map | 2 +
drivers/crypto/mlx5/mlx5_crypto.c | 80 +++++++-----------
drivers/crypto/mlx5/mlx5_crypto.h | 5 +-
drivers/vdpa/mlx5/mlx5_vdpa.h | 5 +-
drivers/vdpa/mlx5/mlx5_vdpa_event.c | 58 ++++---------
7 files changed, 181 insertions(+), 100 deletions(-)
diff --git a/drivers/common/mlx5/mlx5_common_devx.c b/drivers/common/mlx5/mlx5_common_devx.c
index 22c8d356c4..640fe3bbb9 100644
--- a/drivers/common/mlx5/mlx5_common_devx.c
+++ b/drivers/common/mlx5/mlx5_common_devx.c
@@ -271,6 +271,117 @@ mlx5_devx_sq_create(void *ctx, struct mlx5_devx_sq *sq_obj, uint16_t log_wqbb_n,
return -rte_errno;
}
+/**
+ * Destroy DevX Queue Pair.
+ *
+ * @param[in] qp
+ * DevX QP to destroy.
+ */
+void
+mlx5_devx_qp_destroy(struct mlx5_devx_qp *qp)
+{
+ if (qp->qp)
+ claim_zero(mlx5_devx_cmd_destroy(qp->qp));
+ if (qp->umem_obj)
+ claim_zero(mlx5_os_umem_dereg(qp->umem_obj));
+ if (qp->umem_buf)
+ mlx5_free((void *)(uintptr_t)qp->umem_buf);
+}
+
+/**
+ * Create Queue Pair using DevX API.
+ *
+ * Get a pointer to partially initialized attributes structure, and updates the
+ * following fields:
+ * wq_umem_id
+ * wq_umem_offset
+ * dbr_umem_valid
+ * dbr_umem_id
+ * dbr_address
+ * sq_size
+ * log_page_size
+ * rq_size
+ * All other fields are updated by caller.
+ *
+ * @param[in] ctx
+ * Context returned from mlx5 open_device() glue function.
+ * @param[in/out] qp_obj
+ * Pointer to QP to create.
+ * @param[in] log_wqbb_n
+ * Log of number of WQBBs in queue.
+ * @param[in] attr
+ * Pointer to QP attributes structure.
+ * @param[in] socket
+ * Socket to use for allocation.
+ *
+ * @return
+ * 0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_devx_qp_create(void *ctx, struct mlx5_devx_qp *qp_obj, uint16_t log_wqbb_n,
+ struct mlx5_devx_qp_attr *attr, int socket)
+{
+ struct mlx5_devx_obj *qp = NULL;
+ struct mlx5dv_devx_umem *umem_obj = NULL;
+ void *umem_buf = NULL;
+ size_t alignment = MLX5_WQE_BUF_ALIGNMENT;
+ uint32_t umem_size, umem_dbrec;
+ uint16_t qp_size = 1 << log_wqbb_n;
+ int ret;
+
+ if (alignment == (size_t)-1) {
+ DRV_LOG(ERR, "Failed to get WQE buf alignment.");
+ rte_errno = ENOMEM;
+ return -rte_errno;
+ }
+ /* Allocate memory buffer for WQEs and doorbell record. */
+ umem_size = MLX5_WQE_SIZE * qp_size;
+ umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE);
+ umem_size += MLX5_DBR_SIZE;
+ umem_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, umem_size,
+ alignment, socket);
+ if (!umem_buf) {
+ DRV_LOG(ERR, "Failed to allocate memory for QP.");
+ rte_errno = ENOMEM;
+ return -rte_errno;
+ }
+ /* Register allocated buffer in user space with DevX. */
+ umem_obj = mlx5_os_umem_reg(ctx, (void *)(uintptr_t)umem_buf, umem_size,
+ IBV_ACCESS_LOCAL_WRITE);
+ if (!umem_obj) {
+ DRV_LOG(ERR, "Failed to register umem for QP.");
+ rte_errno = errno;
+ goto error;
+ }
+ /* Fill attributes for SQ object creation. */
+ attr->wq_umem_id = mlx5_os_get_umem_id(umem_obj);
+ attr->wq_umem_offset = 0;
+ attr->dbr_umem_valid = 1;
+ attr->dbr_umem_id = attr->wq_umem_id;
+ attr->dbr_address = umem_dbrec;
+ attr->log_page_size = MLX5_LOG_PAGE_SIZE;
+ /* Create send queue object with DevX. */
+ qp = mlx5_devx_cmd_create_qp(ctx, attr);
+ if (!qp) {
+ DRV_LOG(ERR, "Can't create DevX QP object.");
+ rte_errno = ENOMEM;
+ goto error;
+ }
+ qp_obj->umem_buf = umem_buf;
+ qp_obj->umem_obj = umem_obj;
+ qp_obj->qp = qp;
+ qp_obj->db_rec = RTE_PTR_ADD(qp_obj->umem_buf, umem_dbrec);
+ return 0;
+error:
+ ret = rte_errno;
+ if (umem_obj)
+ claim_zero(mlx5_os_umem_dereg(umem_obj));
+ if (umem_buf)
+ mlx5_free((void *)(uintptr_t)umem_buf);
+ rte_errno = ret;
+ return -rte_errno;
+}
+
/**
* Destroy DevX Receive Queue.
*
diff --git a/drivers/common/mlx5/mlx5_common_devx.h b/drivers/common/mlx5/mlx5_common_devx.h
index aad0184e5a..b05260b401 100644
--- a/drivers/common/mlx5/mlx5_common_devx.h
+++ b/drivers/common/mlx5/mlx5_common_devx.h
@@ -33,6 +33,18 @@ struct mlx5_devx_sq {
volatile uint32_t *db_rec; /* The SQ doorbell record. */
};
+/* DevX Queue Pair structure. */
+struct mlx5_devx_qp {
+ struct mlx5_devx_obj *qp; /* The QP DevX object. */
+ void *umem_obj; /* The QP umem object. */
+ union {
+ void *umem_buf;
+ struct mlx5_wqe *wqes; /* The QP ring buffer. */
+ struct mlx5_aso_wqe *aso_wqes;
+ };
+ volatile uint32_t *db_rec; /* The QP doorbell record. */
+};
+
/* DevX Receive Queue structure. */
struct mlx5_devx_rq {
struct mlx5_devx_obj *rq; /* The RQ DevX object. */
@@ -59,6 +71,14 @@ int mlx5_devx_sq_create(void *ctx, struct mlx5_devx_sq *sq_obj,
uint16_t log_wqbb_n,
struct mlx5_devx_create_sq_attr *attr, int socket);
+__rte_internal
+void mlx5_devx_qp_destroy(struct mlx5_devx_qp *qp);
+
+__rte_internal
+int mlx5_devx_qp_create(void *ctx, struct mlx5_devx_qp *qp_obj,
+ uint16_t log_wqbb_n,
+ struct mlx5_devx_qp_attr *attr, int socket);
+
__rte_internal
void mlx5_devx_rq_destroy(struct mlx5_devx_rq *rq);
diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map
index e5cb6b7060..9487f787b6 100644
--- a/drivers/common/mlx5/version.map
+++ b/drivers/common/mlx5/version.map
@@ -71,6 +71,8 @@ INTERNAL {
mlx5_devx_rq_destroy;
mlx5_devx_sq_create;
mlx5_devx_sq_destroy;
+ mlx5_devx_qp_create;
+ mlx5_devx_qp_destroy;
mlx5_free;
diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c
index b3d5200ca3..c66a3a7add 100644
--- a/drivers/crypto/mlx5/mlx5_crypto.c
+++ b/drivers/crypto/mlx5/mlx5_crypto.c
@@ -257,12 +257,12 @@ mlx5_crypto_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)
{
struct mlx5_crypto_qp *qp = dev->data->queue_pairs[qp_id];
- if (qp->qp_obj != NULL)
- claim_zero(mlx5_devx_cmd_destroy(qp->qp_obj));
- if (qp->umem_obj != NULL)
- claim_zero(mlx5_glue->devx_umem_dereg(qp->umem_obj));
- if (qp->umem_buf != NULL)
- rte_free(qp->umem_buf);
+ if (qp->qp_obj.qp != NULL)
+ claim_zero(mlx5_devx_cmd_destroy(qp->qp_obj.qp));
+ if (qp->qp_obj.umem_obj != NULL)
+ claim_zero(mlx5_glue->devx_umem_dereg(qp->qp_obj.umem_obj));
+ if (qp->qp_obj.umem_buf != NULL)
+ rte_free(qp->qp_obj.umem_buf);
mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);
mlx5_devx_cq_destroy(&qp->cq_obj);
rte_free(qp);
@@ -277,20 +277,20 @@ mlx5_crypto_qp2rts(struct mlx5_crypto_qp *qp)
* In Order to configure self loopback, when calling these functions the
* remote QP id that is used is the id of the same QP.
*/
- if (mlx5_devx_cmd_modify_qp_state(qp->qp_obj, MLX5_CMD_OP_RST2INIT_QP,
- qp->qp_obj->id)) {
+ if (mlx5_devx_cmd_modify_qp_state(qp->qp_obj.qp, MLX5_CMD_OP_RST2INIT_QP,
+ qp->qp_obj.qp->id)) {
DRV_LOG(ERR, "Failed to modify QP to INIT state(%u).",
rte_errno);
return -1;
}
- if (mlx5_devx_cmd_modify_qp_state(qp->qp_obj, MLX5_CMD_OP_INIT2RTR_QP,
- qp->qp_obj->id)) {
+ if (mlx5_devx_cmd_modify_qp_state(qp->qp_obj.qp, MLX5_CMD_OP_INIT2RTR_QP,
+ qp->qp_obj.qp->id)) {
DRV_LOG(ERR, "Failed to modify QP to RTR state(%u).",
rte_errno);
return -1;
}
- if (mlx5_devx_cmd_modify_qp_state(qp->qp_obj, MLX5_CMD_OP_RTR2RTS_QP,
- qp->qp_obj->id)) {
+ if (mlx5_devx_cmd_modify_qp_state(qp->qp_obj.qp, MLX5_CMD_OP_RTR2RTS_QP,
+ qp->qp_obj.qp->id)) {
DRV_LOG(ERR, "Failed to modify QP to RTS state(%u).",
rte_errno);
return -1;
@@ -452,7 +452,7 @@ mlx5_crypto_wqe_set(struct mlx5_crypto_priv *priv,
memcpy(klms, &umr->kseg[0], sizeof(*klms) * klm_n);
}
ds = 2 + klm_n;
- cseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj->id << 8) | ds);
+ cseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj.qp->id << 8) | ds);
cseg->opcode = rte_cpu_to_be_32((qp->db_pi << 8) |
MLX5_OPCODE_RDMA_WRITE);
ds = RTE_ALIGN(ds, 4);
@@ -461,7 +461,7 @@ mlx5_crypto_wqe_set(struct mlx5_crypto_priv *priv,
if (priv->max_rdmar_ds > ds) {
cseg += ds;
ds = priv->max_rdmar_ds - ds;
- cseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj->id << 8) | ds);
+ cseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj.qp->id << 8) | ds);
cseg->opcode = rte_cpu_to_be_32((qp->db_pi << 8) |
MLX5_OPCODE_NOP);
qp->db_pi += ds >> 2; /* Here, DS is 4 aligned for sure. */
@@ -503,7 +503,7 @@ mlx5_crypto_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops,
return 0;
do {
op = *ops++;
- umr = RTE_PTR_ADD(qp->umem_buf, priv->wqe_set_size * qp->pi);
+ umr = RTE_PTR_ADD(qp->qp_obj.umem_buf, priv->wqe_set_size * qp->pi);
if (unlikely(mlx5_crypto_wqe_set(priv, qp, op, umr) == 0)) {
qp->stats.enqueue_err_count++;
if (remain != nb_ops) {
@@ -517,7 +517,7 @@ mlx5_crypto_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops,
} while (--remain);
qp->stats.enqueued_count += nb_ops;
rte_io_wmb();
- qp->db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->db_pi);
+ qp->qp_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->db_pi);
rte_wmb();
mlx5_crypto_uar_write(*(volatile uint64_t *)qp->wqe, qp->priv);
rte_wmb();
@@ -583,7 +583,7 @@ mlx5_crypto_qp_init(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp)
uint32_t i;
for (i = 0 ; i < qp->entries_n; i++) {
- struct mlx5_wqe_cseg *cseg = RTE_PTR_ADD(qp->umem_buf, i *
+ struct mlx5_wqe_cseg *cseg = RTE_PTR_ADD(qp->qp_obj.umem_buf, i *
priv->wqe_set_size);
struct mlx5_wqe_umr_cseg *ucseg = (struct mlx5_wqe_umr_cseg *)
(cseg + 1);
@@ -593,7 +593,7 @@ mlx5_crypto_qp_init(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp)
struct mlx5_wqe_rseg *rseg;
/* Init UMR WQE. */
- cseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj->id << 8) |
+ cseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj.qp->id << 8) |
(priv->umr_wqe_size / MLX5_WSEG_SIZE));
cseg->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
MLX5_COMP_MODE_OFFSET);
@@ -628,7 +628,7 @@ mlx5_crypto_indirect_mkeys_prepare(struct mlx5_crypto_priv *priv,
.klm_num = RTE_ALIGN(priv->max_segs_num, 4),
};
- for (umr = (struct mlx5_umr_wqe *)qp->umem_buf, i = 0;
+ for (umr = (struct mlx5_umr_wqe *)qp->qp_obj.umem_buf, i = 0;
i < qp->entries_n; i++, umr = RTE_PTR_ADD(umr, priv->wqe_set_size)) {
attr.klm_array = (struct mlx5_klm *)&umr->kseg[0];
qp->mkey[i] = mlx5_devx_cmd_mkey_create(priv->ctx, &attr);
@@ -649,9 +649,7 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
struct mlx5_devx_qp_attr attr = {0};
struct mlx5_crypto_qp *qp;
uint16_t log_nb_desc = rte_log2_u32(qp_conf->nb_descriptors);
- uint32_t umem_size = RTE_BIT32(log_nb_desc) *
- priv->wqe_set_size +
- sizeof(*qp->db_rec) * 2;
+ uint32_t ret;
uint32_t alloc_size = sizeof(*qp);
struct mlx5_devx_cq_attr cq_attr = {
.uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar),
@@ -675,18 +673,15 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
DRV_LOG(ERR, "Failed to create CQ.");
goto error;
}
- qp->umem_buf = rte_zmalloc_socket(__func__, umem_size, 4096, socket_id);
- if (qp->umem_buf == NULL) {
- DRV_LOG(ERR, "Failed to allocate QP umem.");
- rte_errno = ENOMEM;
- goto error;
- }
- qp->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,
- (void *)(uintptr_t)qp->umem_buf,
- umem_size,
- IBV_ACCESS_LOCAL_WRITE);
- if (qp->umem_obj == NULL) {
- DRV_LOG(ERR, "Failed to register QP umem.");
+ /* fill attributes*/
+ attr.pd = priv->pdn;
+ attr.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar);
+ attr.cqn = qp->cq_obj.cq->id;
+ attr.rq_size = 0;
+ attr.sq_size = RTE_BIT32(log_nb_desc);
+ ret = mlx5_devx_qp_create(priv->ctx, &qp->qp_obj, log_nb_desc, &attr, socket_id);
+ if(ret) {
+ DRV_LOG(ERR, "Failed to create QP");
goto error;
}
if (mlx5_mr_btree_init(&qp->mr_ctrl.cache_bh, MLX5_MR_BTREE_CACHE_N,
@@ -697,23 +692,6 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
goto error;
}
qp->mr_ctrl.dev_gen_ptr = &priv->mr_scache.dev_gen;
- attr.pd = priv->pdn;
- attr.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar);
- attr.cqn = qp->cq_obj.cq->id;
- attr.log_page_size = rte_log2_u32(sysconf(_SC_PAGESIZE));
- attr.rq_size = 0;
- attr.sq_size = RTE_BIT32(log_nb_desc);
- attr.dbr_umem_valid = 1;
- attr.wq_umem_id = qp->umem_obj->umem_id;
- attr.wq_umem_offset = 0;
- attr.dbr_umem_id = qp->umem_obj->umem_id;
- attr.dbr_address = RTE_BIT64(log_nb_desc) * priv->wqe_set_size;
- qp->qp_obj = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
- if (qp->qp_obj == NULL) {
- DRV_LOG(ERR, "Failed to create QP(%u).", rte_errno);
- goto error;
- }
- qp->db_rec = RTE_PTR_ADD(qp->umem_buf, (uintptr_t)attr.dbr_address);
if (mlx5_crypto_qp2rts(qp))
goto error;
qp->mkey = (struct mlx5_devx_obj **)RTE_ALIGN((uintptr_t)(qp + 1),
diff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h
index d49b0001f0..013eed30b5 100644
--- a/drivers/crypto/mlx5/mlx5_crypto.h
+++ b/drivers/crypto/mlx5/mlx5_crypto.h
@@ -43,11 +43,8 @@ struct mlx5_crypto_priv {
struct mlx5_crypto_qp {
struct mlx5_crypto_priv *priv;
struct mlx5_devx_cq cq_obj;
- struct mlx5_devx_obj *qp_obj;
+ struct mlx5_devx_qp qp_obj;
struct rte_cryptodev_stats stats;
- struct mlx5dv_devx_umem *umem_obj;
- void *umem_buf;
- volatile uint32_t *db_rec;
struct rte_crypto_op **ops;
struct mlx5_devx_obj **mkey; /* WQE's indirect mekys. */
struct mlx5_mr_ctrl mr_ctrl;
diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h
index 2a04e36607..a27f3fdadb 100644
--- a/drivers/vdpa/mlx5/mlx5_vdpa.h
+++ b/drivers/vdpa/mlx5/mlx5_vdpa.h
@@ -54,10 +54,7 @@ struct mlx5_vdpa_cq {
struct mlx5_vdpa_event_qp {
struct mlx5_vdpa_cq cq;
struct mlx5_devx_obj *fw_qp;
- struct mlx5_devx_obj *sw_qp;
- struct mlx5dv_devx_umem *umem_obj;
- void *umem_buf;
- volatile uint32_t *db_rec;
+ struct mlx5_devx_qp sw_qp;
};
struct mlx5_vdpa_query_mr {
diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_event.c b/drivers/vdpa/mlx5/mlx5_vdpa_event.c
index 3541c652ce..d327a605fa 100644
--- a/drivers/vdpa/mlx5/mlx5_vdpa_event.c
+++ b/drivers/vdpa/mlx5/mlx5_vdpa_event.c
@@ -179,7 +179,7 @@ mlx5_vdpa_cq_poll(struct mlx5_vdpa_cq *cq)
cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
rte_io_wmb();
/* Ring SW QP doorbell record. */
- eqp->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci + cq_size);
+ eqp->sw_qp.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci + cq_size);
}
return comp;
}
@@ -531,12 +531,12 @@ mlx5_vdpa_cqe_event_unset(struct mlx5_vdpa_priv *priv)
void
mlx5_vdpa_event_qp_destroy(struct mlx5_vdpa_event_qp *eqp)
{
- if (eqp->sw_qp)
- claim_zero(mlx5_devx_cmd_destroy(eqp->sw_qp));
- if (eqp->umem_obj)
- claim_zero(mlx5_glue->devx_umem_dereg(eqp->umem_obj));
- if (eqp->umem_buf)
- rte_free(eqp->umem_buf);
+ if (eqp->sw_qp.qp)
+ claim_zero(mlx5_devx_cmd_destroy(eqp->sw_qp.qp));
+ if (eqp->sw_qp.umem_obj)
+ claim_zero(mlx5_glue->devx_umem_dereg(eqp->sw_qp.umem_obj));
+ if (eqp->sw_qp.umem_buf)
+ rte_free(eqp->sw_qp.umem_buf);
if (eqp->fw_qp)
claim_zero(mlx5_devx_cmd_destroy(eqp->fw_qp));
mlx5_vdpa_cq_destroy(&eqp->cq);
@@ -547,36 +547,36 @@ static int
mlx5_vdpa_qps2rts(struct mlx5_vdpa_event_qp *eqp)
{
if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RST2INIT_QP,
- eqp->sw_qp->id)) {
+ eqp->sw_qp.qp->id)) {
DRV_LOG(ERR, "Failed to modify FW QP to INIT state(%u).",
rte_errno);
return -1;
}
- if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RST2INIT_QP,
+ if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp.qp, MLX5_CMD_OP_RST2INIT_QP,
eqp->fw_qp->id)) {
DRV_LOG(ERR, "Failed to modify SW QP to INIT state(%u).",
rte_errno);
return -1;
}
if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_INIT2RTR_QP,
- eqp->sw_qp->id)) {
+ eqp->sw_qp.qp->id)) {
DRV_LOG(ERR, "Failed to modify FW QP to RTR state(%u).",
rte_errno);
return -1;
}
- if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_INIT2RTR_QP,
+ if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp.qp, MLX5_CMD_OP_INIT2RTR_QP,
eqp->fw_qp->id)) {
DRV_LOG(ERR, "Failed to modify SW QP to RTR state(%u).",
rte_errno);
return -1;
}
if (mlx5_devx_cmd_modify_qp_state(eqp->fw_qp, MLX5_CMD_OP_RTR2RTS_QP,
- eqp->sw_qp->id)) {
+ eqp->sw_qp.qp->id)) {
DRV_LOG(ERR, "Failed to modify FW QP to RTS state(%u).",
rte_errno);
return -1;
}
- if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp, MLX5_CMD_OP_RTR2RTS_QP,
+ if (mlx5_devx_cmd_modify_qp_state(eqp->sw_qp.qp, MLX5_CMD_OP_RTR2RTS_QP,
eqp->fw_qp->id)) {
DRV_LOG(ERR, "Failed to modify SW QP to RTS state(%u).",
rte_errno);
@@ -591,8 +591,7 @@ mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n,
{
struct mlx5_devx_qp_attr attr = {0};
uint16_t log_desc_n = rte_log2_u32(desc_n);
- uint32_t umem_size = (1 << log_desc_n) * MLX5_WSEG_SIZE +
- sizeof(*eqp->db_rec) * 2;
+ uint32_t ret;
if (mlx5_vdpa_event_qp_global_prepare(priv))
return -1;
@@ -605,42 +604,19 @@ mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n,
DRV_LOG(ERR, "Failed to create FW QP(%u).", rte_errno);
goto error;
}
- eqp->umem_buf = rte_zmalloc(__func__, umem_size, 4096);
- if (!eqp->umem_buf) {
- DRV_LOG(ERR, "Failed to allocate memory for SW QP.");
- rte_errno = ENOMEM;
- goto error;
- }
- eqp->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,
- (void *)(uintptr_t)eqp->umem_buf,
- umem_size,
- IBV_ACCESS_LOCAL_WRITE);
- if (!eqp->umem_obj) {
- DRV_LOG(ERR, "Failed to register umem for SW QP.");
- goto error;
- }
- attr.uar_index = priv->uar->page_id;
- attr.cqn = eqp->cq.cq_obj.cq->id;
- attr.log_page_size = rte_log2_u32(sysconf(_SC_PAGESIZE));
attr.rq_size = 1 << log_desc_n;
attr.log_rq_stride = rte_log2_u32(MLX5_WSEG_SIZE);
attr.sq_size = 0; /* No need SQ. */
- attr.dbr_umem_valid = 1;
- attr.wq_umem_id = eqp->umem_obj->umem_id;
- attr.wq_umem_offset = 0;
- attr.dbr_umem_id = eqp->umem_obj->umem_id;
attr.ts_format = mlx5_ts_format_conv(priv->qp_ts_format);
- attr.dbr_address = RTE_BIT64(log_desc_n) * MLX5_WSEG_SIZE;
- eqp->sw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr);
- if (!eqp->sw_qp) {
+ ret = mlx5_devx_qp_create(priv->ctx, &(eqp->sw_qp), log_desc_n, &attr, SOCKET_ID_ANY);
+ if (ret) {
DRV_LOG(ERR, "Failed to create SW QP(%u).", rte_errno);
goto error;
}
- eqp->db_rec = RTE_PTR_ADD(eqp->umem_buf, (uintptr_t)attr.dbr_address);
if (mlx5_vdpa_qps2rts(eqp))
goto error;
/* First ringing. */
- rte_write32(rte_cpu_to_be_32(1 << log_desc_n), &eqp->db_rec[0]);
+ rte_write32(rte_cpu_to_be_32(1 << log_desc_n), &eqp->sw_qp.db_rec[0]);
return 0;
error:
mlx5_vdpa_event_qp_destroy(eqp);
--
2.27.0
^ permalink raw reply [flat|nested] 4+ messages in thread* [dpdk-dev] [RFC 2/3] compress/mlx5: refactor queue creation in mlx5 add support to compress and regex drivers in BlueField3
2021-08-18 15:14 [dpdk-dev] [RFC 0/3] mlx5: replaced hardware queue object Raja Zidane
2021-08-18 15:14 ` [dpdk-dev] [RFC 1/3] common/mlx5: add common qp_create Raja Zidane
@ 2021-08-18 15:14 ` Raja Zidane
2021-08-18 15:14 ` [dpdk-dev] [RFC 3/3] regex/mlx5: refactor queue creation in mlx5 add support to compress and regex drivers in Bluefield3 Raja Zidane
2 siblings, 0 replies; 4+ messages in thread
From: Raja Zidane @ 2021-08-18 15:14 UTC (permalink / raw)
To: dev; +Cc: matan, orika
Signed-off-by: Raja Zidane <rzidane@nvidia.com>
---
drivers/common/mlx5/mlx5_devx_cmds.c | 14 ++++-
drivers/common/mlx5/mlx5_devx_cmds.h | 10 ++-
drivers/common/mlx5/mlx5_prm.h | 42 +++++++++++--
drivers/compress/mlx5/mlx5_compress.c | 91 ++++++++++++++++++---------
4 files changed, 116 insertions(+), 41 deletions(-)
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index 56407cc332..347ae75d37 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -858,9 +858,12 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);
attr->reg_c_preserve =
MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve);
- attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo);
- attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress);
- attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress);
+ attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq);
+ attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, compress_mmo_sq);
+ attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, decompress_mmo_sq);
+ attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp);
+ attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, compress_mmo_qp);
+ attr->mmo_decompress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, decompress_mmo_qp);
attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,
compress_min_block_size);
attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);
@@ -2022,6 +2025,11 @@ mlx5_devx_cmd_create_qp(void *ctx,
MLX5_SET(qpc, qpc, pd, attr->pd);
MLX5_SET(qpc, qpc, ts_format, attr->ts_format);
if (attr->uar_index) {
+ if(attr->mmo) {
+ void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, in, qpc_extension_and_pas_list);
+ void* qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, qpc_ext_and_pas_list, qpc_data_extension);
+ MLX5_SET(qpc_extension, qpc_ext, mmo, 1);
+ }
MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index e576e30f24..f993b511dc 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -173,9 +173,12 @@ struct mlx5_hca_attr {
uint32_t log_max_srq;
uint32_t log_max_srq_sz;
uint32_t rss_ind_tbl_cap;
- uint32_t mmo_dma_en:1;
- uint32_t mmo_compress_en:1;
- uint32_t mmo_decompress_en:1;
+ uint32_t mmo_dma_sq_en:1;
+ uint32_t mmo_compress_sq_en:1;
+ uint32_t mmo_decompress_sq_en:1;
+ uint32_t mmo_dma_qp_en:1;
+ uint32_t mmo_compress_qp_en:1;
+ uint32_t mmo_decompress_qp_en:1;
uint32_t compress_min_block_size:4;
uint32_t log_max_mmo_dma:5;
uint32_t log_max_mmo_compress:5;
@@ -397,6 +400,7 @@ struct mlx5_devx_qp_attr {
uint64_t dbr_address;
uint32_t wq_umem_id;
uint64_t wq_umem_offset;
+ uint32_t mmo;
};
struct mlx5_devx_virtio_q_couners_attr {
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index fdb20f5d49..d0c75b97df 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -1385,10 +1385,10 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 rtr2rts_qp_counters_set_id[0x1];
u8 rts2rts_udp_sport[0x1];
u8 rts2rts_lag_tx_port_affinity[0x1];
- u8 dma_mmo[0x1];
+ u8 dma_mmo_sq[0x1];
u8 compress_min_block_size[0x4];
- u8 compress[0x1];
- u8 decompress[0x1];
+ u8 compress_mmo_sq[0x1];
+ u8 decompress_mmo_sq[0x1];
u8 log_max_ra_res_qp[0x6];
u8 end_pad[0x1];
u8 cc_query_allowed[0x1];
@@ -1631,7 +1631,12 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 num_vhca_ports[0x8];
u8 reserved_at_618[0x6];
u8 sw_owner_id[0x1];
- u8 reserved_at_61f[0x1e1];
+ u8 reserved_at_61f[0x109];
+ u8 dma_mmo_qp[0x1];
+ u8 reserved_at_621[0x1];
+ u8 compress_mmo_qp[0x1];
+ u8 decompress_mmo_qp[0x1];
+ u8 reserved_at_624[0xd4];
};
struct mlx5_ifc_qos_cap_bits {
@@ -3235,6 +3240,27 @@ struct mlx5_ifc_create_qp_out_bits {
u8 reserved_at_60[0x20];
};
+struct mlx5_ifc_qpc_extension_bits {
+ u8 reserved_at_0[0x2];
+ u8 mmo[0x1];
+ u8 reserved_at_3[0x5fd];
+};
+
+#ifdef PEDANTIC
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+struct mlx5_ifc_qpc_pas_list_bits {
+ u8 pas[0][0x40];
+};
+
+#ifdef PEDANTIC
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+struct mlx5_ifc_qpc_extension_and_pas_list_bits {
+ struct mlx5_ifc_qpc_extension_bits qpc_data_extension;
+ u8 pas[0][0x40];
+};
+
#ifdef PEDANTIC
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
@@ -3243,7 +3269,8 @@ struct mlx5_ifc_create_qp_in_bits {
u8 uid[0x10];
u8 reserved_at_20[0x10];
u8 op_mod[0x10];
- u8 reserved_at_40[0x40];
+ u8 qpc_ext[0x1];
+ u8 reserved_at_41[0x3f];
u8 opt_param_mask[0x20];
u8 reserved_at_a0[0x20];
struct mlx5_ifc_qpc_bits qpc;
@@ -3251,7 +3278,10 @@ struct mlx5_ifc_create_qp_in_bits {
u8 wq_umem_id[0x20];
u8 wq_umem_valid[0x1];
u8 reserved_at_861[0x1f];
- u8 pas[0][0x40];
+ union {
+ struct mlx5_ifc_qpc_pas_list_bits qpc_pas_list;
+ struct mlx5_ifc_qpc_extension_and_pas_list_bits qpc_extension_and_pas_list;
+ };
};
#ifdef PEDANTIC
#pragma GCC diagnostic error "-Wpedantic"
diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c
index 883e720ec1..05e75adb1c 100644
--- a/drivers/compress/mlx5/mlx5_compress.c
+++ b/drivers/compress/mlx5/mlx5_compress.c
@@ -48,6 +48,7 @@ struct mlx5_compress_priv {
rte_spinlock_t xform_sl;
struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */
volatile uint64_t *uar_addr;
+ uint8_t mmo_caps; /* bitmap 0->5: decomp_sq, decomp_qp, comp_sq, comp_qp, dma_sq, dma_qp */
#ifndef RTE_ARCH_64
rte_spinlock_t uar32_sl;
#endif /* RTE_ARCH_64 */
@@ -61,7 +62,7 @@ struct mlx5_compress_qp {
struct mlx5_mr_ctrl mr_ctrl;
int socket_id;
struct mlx5_devx_cq cq;
- struct mlx5_devx_sq sq;
+ struct mlx5_devx_qp qp;
struct mlx5_pmd_mr opaque_mr;
struct rte_comp_op **ops;
struct mlx5_compress_priv *priv;
@@ -134,8 +135,8 @@ mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id)
{
struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
- if (qp->sq.sq != NULL)
- mlx5_devx_sq_destroy(&qp->sq);
+ if (qp->qp.qp != NULL)
+ mlx5_devx_qp_destroy(&qp->qp);
if (qp->cq.cq != NULL)
mlx5_devx_cq_destroy(&qp->cq);
if (qp->opaque_mr.obj != NULL) {
@@ -152,12 +153,12 @@ mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id)
}
static void
-mlx5_compress_init_sq(struct mlx5_compress_qp *qp)
+mlx5_compress_init_qp(struct mlx5_compress_qp *qp)
{
volatile struct mlx5_gga_wqe *restrict wqe =
- (volatile struct mlx5_gga_wqe *)qp->sq.wqes;
+ (volatile struct mlx5_gga_wqe *)qp->qp.wqes;
volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
- const uint32_t sq_ds = rte_cpu_to_be_32((qp->sq.sq->id << 8) | 4u);
+ const uint32_t sq_ds = rte_cpu_to_be_32((qp->qp.qp->id << 8) | 4u);
const uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS <<
MLX5_COMP_MODE_OFFSET);
const uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey);
@@ -173,6 +174,35 @@ mlx5_compress_init_sq(struct mlx5_compress_qp *qp)
}
}
+static int
+mlx5_compress_qp2rts(struct mlx5_compress_qp *qp)
+{
+ /*
+ * In Order to configure self loopback, when calling these functions the
+ * remote QP id that is used is the id of the same QP.
+ */
+ if (mlx5_devx_cmd_modify_qp_state(qp->qp.qp, MLX5_CMD_OP_RST2INIT_QP,
+ qp->qp.qp->id)) {
+ DRV_LOG(ERR, "Failed to modify QP to INIT state(%u).",
+ rte_errno);
+ return -1;
+ }
+ if (mlx5_devx_cmd_modify_qp_state(qp->qp.qp, MLX5_CMD_OP_INIT2RTR_QP,
+ qp->qp.qp->id)) {
+ DRV_LOG(ERR, "Failed to modify QP to RTR state(%u).",
+ rte_errno);
+ return -1;
+ }
+ if (mlx5_devx_cmd_modify_qp_state(qp->qp.qp, MLX5_CMD_OP_RTR2RTS_QP,
+ qp->qp.qp->id)) {
+ DRV_LOG(ERR, "Failed to modify QP to RTS state(%u).",
+ rte_errno);
+ return -1;
+ }
+ return 0;
+}
+
+
static int
mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
uint32_t max_inflight_ops, int socket_id)
@@ -182,15 +212,9 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
struct mlx5_devx_cq_attr cq_attr = {
.uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar),
};
- struct mlx5_devx_create_sq_attr sq_attr = {
- .user_index = qp_id,
- .wq_attr = (struct mlx5_devx_wq_attr){
- .pd = priv->pdn,
- .uar_page = mlx5_os_get_devx_uar_page_id(priv->uar),
- },
- };
- struct mlx5_devx_modify_sq_attr modify_attr = {
- .state = MLX5_SQC_STATE_RDY,
+ struct mlx5_devx_qp_attr qp_attr = {
+ .pd = priv->pdn,
+ .uar_index = mlx5_os_get_devx_uar_page_id(priv->uar),
};
uint32_t log_ops_n = rte_log2_u32(max_inflight_ops);
uint32_t alloc_size = sizeof(*qp);
@@ -242,24 +266,26 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
DRV_LOG(ERR, "Failed to create CQ.");
goto err;
}
- sq_attr.cqn = qp->cq.cq->id;
- sq_attr.ts_format = mlx5_ts_format_conv(priv->sq_ts_format);
- ret = mlx5_devx_sq_create(priv->ctx, &qp->sq, log_ops_n, &sq_attr,
+ qp_attr.cqn = qp->cq.cq->id;
+ qp_attr.ts_format = mlx5_ts_format_conv(priv->sq_ts_format);
+ qp_attr.rq_size = 0;
+ qp_attr.sq_size = 1 << log_ops_n;
+ qp_attr.mmo = (priv->mmo_caps & (1<<1)) && (priv->mmo_caps & (1<<3)) && (priv->mmo_caps & (1<<5));
+ ret = mlx5_devx_qp_create(priv->ctx, &qp->qp, log_ops_n, &qp_attr,
socket_id);
if (ret != 0) {
- DRV_LOG(ERR, "Failed to create SQ.");
+ DRV_LOG(ERR, "Failed to create QP.");
goto err;
}
- mlx5_compress_init_sq(qp);
- ret = mlx5_devx_cmd_modify_sq(qp->sq.sq, &modify_attr);
- if (ret != 0) {
- DRV_LOG(ERR, "Can't change SQ state to ready.");
+ ret = mlx5_compress_qp2rts(qp);
+ if(ret) {
goto err;
}
+ mlx5_compress_init_qp(qp);
/* Save pointer of global generation number to check memory event. */
qp->mr_ctrl.dev_gen_ptr = &priv->mr_scache.dev_gen;
DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u",
- (uint32_t)qp_id, qp->sq.sq->id, qp->cq.cq->id, qp->entries_n);
+ (uint32_t)qp_id, qp->qp.qp->id, qp->cq.cq->id, qp->entries_n);
return 0;
err:
mlx5_compress_qp_release(dev, qp_id);
@@ -508,7 +534,7 @@ mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops,
{
struct mlx5_compress_qp *qp = queue_pair;
volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
- qp->sq.wqes, *wqe;
+ qp->qp.wqes, *wqe;
struct mlx5_compress_xform *xform;
struct rte_comp_op *op;
uint16_t mask = qp->entries_n - 1;
@@ -563,7 +589,7 @@ mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops,
} while (--remain);
qp->stats.enqueued_count += nb_ops;
rte_io_wmb();
- qp->sq.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->pi);
+ qp->qp.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->pi);
rte_wmb();
mlx5_compress_uar_write(*(volatile uint64_t *)wqe, qp->priv);
rte_wmb();
@@ -598,7 +624,7 @@ mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp,
volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *)
&qp->cq.cqes[idx];
volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
- qp->sq.wqes;
+ qp->qp.wqes;
volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
op->status = RTE_COMP_OP_STATUS_ERROR;
@@ -813,8 +839,9 @@ mlx5_compress_dev_probe(struct rte_device *dev)
return -rte_errno;
}
if (mlx5_devx_cmd_query_hca_attr(ctx, &att) != 0 ||
- att.mmo_compress_en == 0 || att.mmo_decompress_en == 0 ||
- att.mmo_dma_en == 0) {
+ ((att.mmo_compress_sq_en == 0 || att.mmo_decompress_sq_en == 0 ||
+ att.mmo_dma_sq_en == 0) && (att.mmo_compress_qp_en == 0 ||
+ att.mmo_decompress_qp_en == 0 || att.mmo_dma_qp_en == 0))) {
DRV_LOG(ERR, "Not enough capabilities to support compress "
"operations, maybe old FW/OFED version?");
claim_zero(mlx5_glue->close_device(ctx));
@@ -835,6 +862,12 @@ mlx5_compress_dev_probe(struct rte_device *dev)
cdev->enqueue_burst = mlx5_compress_enqueue_burst;
cdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
priv = cdev->data->dev_private;
+ priv->mmo_caps = 0 | att.mmo_decompress_sq_en;
+ priv->mmo_caps |= att.mmo_decompress_qp_en << 1;
+ priv->mmo_caps |= att.mmo_compress_sq_en << 2;
+ priv->mmo_caps |= att.mmo_compress_qp_en << 3;
+ priv->mmo_caps |= att.mmo_dma_sq_en << 4;
+ priv->mmo_caps |= att.mmo_dma_qp_en << 5;
priv->ctx = ctx;
priv->cdev = cdev;
priv->min_block_size = att.compress_min_block_size;
--
2.27.0
^ permalink raw reply [flat|nested] 4+ messages in thread* [dpdk-dev] [RFC 3/3] regex/mlx5: refactor queue creation in mlx5 add support to compress and regex drivers in Bluefield3
2021-08-18 15:14 [dpdk-dev] [RFC 0/3] mlx5: replaced hardware queue object Raja Zidane
2021-08-18 15:14 ` [dpdk-dev] [RFC 1/3] common/mlx5: add common qp_create Raja Zidane
2021-08-18 15:14 ` [dpdk-dev] [RFC 2/3] compress/mlx5: refactor queue creation in mlx5 add support to compress and regex drivers in BlueField3 Raja Zidane
@ 2021-08-18 15:14 ` Raja Zidane
2 siblings, 0 replies; 4+ messages in thread
From: Raja Zidane @ 2021-08-18 15:14 UTC (permalink / raw)
To: dev; +Cc: matan, orika
Signed-off-by: Raja Zidane <rzidane@nvidia.com>
---
drivers/common/mlx5/mlx5_common_devx.c | 28 ++++++++++++
drivers/common/mlx5/mlx5_common_devx.h | 3 ++
drivers/common/mlx5/version.map | 1 +
drivers/compress/mlx5/mlx5_compress.c | 31 +------------
drivers/crypto/mlx5/mlx5_crypto.c | 30 +------------
drivers/regex/mlx5/mlx5_regex.h | 6 +--
drivers/regex/mlx5/mlx5_regex_control.c | 60 ++++++++++++-------------
7 files changed, 65 insertions(+), 94 deletions(-)
diff --git a/drivers/common/mlx5/mlx5_common_devx.c b/drivers/common/mlx5/mlx5_common_devx.c
index 640fe3bbb9..0baf0831e8 100644
--- a/drivers/common/mlx5/mlx5_common_devx.c
+++ b/drivers/common/mlx5/mlx5_common_devx.c
@@ -496,3 +496,31 @@ mlx5_devx_rq_create(void *ctx, struct mlx5_devx_rq *rq_obj, uint32_t wqe_size,
return -rte_errno;
}
+int
+mlx5_devx_qp2rts(struct mlx5_devx_qp *qp)
+{
+ /*
+ * In Order to configure self loopback, when calling these functions the
+ * remote QP id that is used is the id of the same QP.
+ */
+ if (mlx5_devx_cmd_modify_qp_state(qp->qp, MLX5_CMD_OP_RST2INIT_QP,
+ qp->qp->id)) {
+ DRV_LOG(ERR, "Failed to modify QP to INIT state(%u).",
+ rte_errno);
+ return -1;
+ }
+ if (mlx5_devx_cmd_modify_qp_state(qp->qp, MLX5_CMD_OP_INIT2RTR_QP,
+ qp->qp->id)) {
+ DRV_LOG(ERR, "Failed to modify QP to RTR state(%u).",
+ rte_errno);
+ return -1;
+ }
+ if (mlx5_devx_cmd_modify_qp_state(qp->qp, MLX5_CMD_OP_RTR2RTS_QP,
+ qp->qp->id)) {
+ DRV_LOG(ERR, "Failed to modify QP to RTS state(%u).",
+ rte_errno);
+ return -1;
+ }
+ return 0;
+}
+
diff --git a/drivers/common/mlx5/mlx5_common_devx.h b/drivers/common/mlx5/mlx5_common_devx.h
index b05260b401..81036f92ff 100644
--- a/drivers/common/mlx5/mlx5_common_devx.h
+++ b/drivers/common/mlx5/mlx5_common_devx.h
@@ -87,4 +87,7 @@ int mlx5_devx_rq_create(void *ctx, struct mlx5_devx_rq *rq_obj,
uint32_t wqe_size, uint16_t log_wqbb_n,
struct mlx5_devx_create_rq_attr *attr, int socket);
+__rte_internal
+int mlx5_devx_qp2rts(struct mlx5_devx_qp *qp);
+
#endif /* RTE_PMD_MLX5_COMMON_DEVX_H_ */
diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map
index 9487f787b6..e61673dcb0 100644
--- a/drivers/common/mlx5/version.map
+++ b/drivers/common/mlx5/version.map
@@ -73,6 +73,7 @@ INTERNAL {
mlx5_devx_sq_destroy;
mlx5_devx_qp_create;
mlx5_devx_qp_destroy;
+ mlx5_devx_qp2rts;
mlx5_free;
diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c
index 05e75adb1c..9cf75a9193 100644
--- a/drivers/compress/mlx5/mlx5_compress.c
+++ b/drivers/compress/mlx5/mlx5_compress.c
@@ -174,35 +174,6 @@ mlx5_compress_init_qp(struct mlx5_compress_qp *qp)
}
}
-static int
-mlx5_compress_qp2rts(struct mlx5_compress_qp *qp)
-{
- /*
- * In Order to configure self loopback, when calling these functions the
- * remote QP id that is used is the id of the same QP.
- */
- if (mlx5_devx_cmd_modify_qp_state(qp->qp.qp, MLX5_CMD_OP_RST2INIT_QP,
- qp->qp.qp->id)) {
- DRV_LOG(ERR, "Failed to modify QP to INIT state(%u).",
- rte_errno);
- return -1;
- }
- if (mlx5_devx_cmd_modify_qp_state(qp->qp.qp, MLX5_CMD_OP_INIT2RTR_QP,
- qp->qp.qp->id)) {
- DRV_LOG(ERR, "Failed to modify QP to RTR state(%u).",
- rte_errno);
- return -1;
- }
- if (mlx5_devx_cmd_modify_qp_state(qp->qp.qp, MLX5_CMD_OP_RTR2RTS_QP,
- qp->qp.qp->id)) {
- DRV_LOG(ERR, "Failed to modify QP to RTS state(%u).",
- rte_errno);
- return -1;
- }
- return 0;
-}
-
-
static int
mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
uint32_t max_inflight_ops, int socket_id)
@@ -277,7 +248,7 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
DRV_LOG(ERR, "Failed to create QP.");
goto err;
}
- ret = mlx5_compress_qp2rts(qp);
+ ret = mlx5_devx_qp2rts(&qp->qp);
if(ret) {
goto err;
}
diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c
index c66a3a7add..94023e4844 100644
--- a/drivers/crypto/mlx5/mlx5_crypto.c
+++ b/drivers/crypto/mlx5/mlx5_crypto.c
@@ -270,34 +270,6 @@ mlx5_crypto_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)
return 0;
}
-static int
-mlx5_crypto_qp2rts(struct mlx5_crypto_qp *qp)
-{
- /*
- * In Order to configure self loopback, when calling these functions the
- * remote QP id that is used is the id of the same QP.
- */
- if (mlx5_devx_cmd_modify_qp_state(qp->qp_obj.qp, MLX5_CMD_OP_RST2INIT_QP,
- qp->qp_obj.qp->id)) {
- DRV_LOG(ERR, "Failed to modify QP to INIT state(%u).",
- rte_errno);
- return -1;
- }
- if (mlx5_devx_cmd_modify_qp_state(qp->qp_obj.qp, MLX5_CMD_OP_INIT2RTR_QP,
- qp->qp_obj.qp->id)) {
- DRV_LOG(ERR, "Failed to modify QP to RTR state(%u).",
- rte_errno);
- return -1;
- }
- if (mlx5_devx_cmd_modify_qp_state(qp->qp_obj.qp, MLX5_CMD_OP_RTR2RTS_QP,
- qp->qp_obj.qp->id)) {
- DRV_LOG(ERR, "Failed to modify QP to RTS state(%u).",
- rte_errno);
- return -1;
- }
- return 0;
-}
-
static __rte_noinline uint32_t
mlx5_crypto_get_block_size(struct rte_crypto_op *op)
{
@@ -692,7 +664,7 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
goto error;
}
qp->mr_ctrl.dev_gen_ptr = &priv->mr_scache.dev_gen;
- if (mlx5_crypto_qp2rts(qp))
+ if (mlx5_devx_qp2rts(&qp->qp_obj))
goto error;
qp->mkey = (struct mlx5_devx_obj **)RTE_ALIGN((uintptr_t)(qp + 1),
RTE_CACHE_LINE_SIZE);
diff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h
index 514f3408f9..41ed58a6af 100644
--- a/drivers/regex/mlx5/mlx5_regex.h
+++ b/drivers/regex/mlx5/mlx5_regex.h
@@ -17,9 +17,9 @@
#include "mlx5_rxp.h"
#include "mlx5_regex_utils.h"
-struct mlx5_regex_sq {
+struct mlx5_regex_inner_qp {
uint16_t log_nb_desc; /* Log 2 number of desc for this object. */
- struct mlx5_devx_sq sq_obj; /* The SQ DevX object. */
+ struct mlx5_devx_qp qp_obj; /* The QP DevX object. */
size_t pi, db_pi;
size_t ci;
uint32_t sqn;
@@ -34,7 +34,7 @@ struct mlx5_regex_cq {
struct mlx5_regex_qp {
uint32_t flags; /* QP user flags. */
uint32_t nb_desc; /* Total number of desc for this qp. */
- struct mlx5_regex_sq *sqs; /* Pointer to sq array. */
+ struct mlx5_regex_inner_qp *qps; /* Pointer to qp array. */
uint16_t nb_obj; /* Number of sq objects. */
struct mlx5_regex_cq cq; /* CQ struct. */
uint32_t free_sqs;
diff --git a/drivers/regex/mlx5/mlx5_regex_control.c b/drivers/regex/mlx5/mlx5_regex_control.c
index 8ce2dabb55..353d6aec97 100644
--- a/drivers/regex/mlx5/mlx5_regex_control.c
+++ b/drivers/regex/mlx5/mlx5_regex_control.c
@@ -106,12 +106,12 @@ regex_ctrl_create_cq(struct mlx5_regex_priv *priv, struct mlx5_regex_cq *cq)
* 0 on success, a negative errno value otherwise and rte_errno is set.
*/
static int
-regex_ctrl_destroy_sq(struct mlx5_regex_qp *qp, uint16_t q_ind)
+regex_ctrl_destroy_inner_qp(struct mlx5_regex_qp *qp, uint16_t q_ind)
{
- struct mlx5_regex_sq *sq = &qp->sqs[q_ind];
+ struct mlx5_regex_inner_qp *qp_obj = &qp->qps[q_ind];
- mlx5_devx_sq_destroy(&sq->sq_obj);
- memset(sq, 0, sizeof(*sq));
+ mlx5_devx_qp_destroy(&qp_obj->qp_obj);
+ memset(qp, 0, sizeof(*qp));
return 0;
}
@@ -131,45 +131,41 @@ regex_ctrl_destroy_sq(struct mlx5_regex_qp *qp, uint16_t q_ind)
* 0 on success, a negative errno value otherwise and rte_errno is set.
*/
static int
-regex_ctrl_create_sq(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp,
+regex_ctrl_create_inner_qp(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp,
uint16_t q_ind, uint16_t log_nb_desc)
{
#ifdef HAVE_IBV_FLOW_DV_SUPPORT
- struct mlx5_devx_create_sq_attr attr = {
- .user_index = q_ind,
+ struct mlx5_devx_qp_attr attr = {
.cqn = qp->cq.cq_obj.cq->id,
- .wq_attr = (struct mlx5_devx_wq_attr){
- .uar_page = priv->uar->page_id,
- },
+ .uar_index = priv->uar->page_id,
.ts_format = mlx5_ts_format_conv(priv->sq_ts_format),
};
- struct mlx5_devx_modify_sq_attr modify_attr = {
- .state = MLX5_SQC_STATE_RDY,
- };
- struct mlx5_regex_sq *sq = &qp->sqs[q_ind];
+ struct mlx5_regex_inner_qp *qp_obj = &qp->qps[q_ind];
uint32_t pd_num = 0;
int ret;
- sq->log_nb_desc = log_nb_desc;
- sq->sqn = q_ind;
- sq->ci = 0;
- sq->pi = 0;
+ qp_obj->log_nb_desc = log_nb_desc;
+ qp_obj->sqn = q_ind;
+ qp_obj->ci = 0;
+ qp_obj->pi = 0;
ret = regex_get_pdn(priv->pd, &pd_num);
if (ret)
return ret;
- attr.wq_attr.pd = pd_num;
- ret = mlx5_devx_sq_create(priv->ctx, &sq->sq_obj,
+ attr.pd = pd_num;
+ attr.rq_size = 0;
+ attr.sq_size = 1 << log_nb_desc;
+ ret = mlx5_devx_qp_create(priv->ctx, &qp_obj->qp_obj,
MLX5_REGEX_WQE_LOG_NUM(priv->has_umr, log_nb_desc),
&attr, SOCKET_ID_ANY);
if (ret) {
- DRV_LOG(ERR, "Can't create SQ object.");
+ DRV_LOG(ERR, "Can't create QP object.");
rte_errno = ENOMEM;
return -rte_errno;
}
- ret = mlx5_devx_cmd_modify_sq(sq->sq_obj.sq, &modify_attr);
+ ret = mlx5_devx_qp2rts(&qp_obj->qp_obj);
if (ret) {
- DRV_LOG(ERR, "Can't change SQ state to ready.");
- regex_ctrl_destroy_sq(qp, q_ind);
+ DRV_LOG(ERR, "Can't change QP state to RTS.");
+ regex_ctrl_destroy_inner_qp(qp, q_ind);
rte_errno = ENOMEM;
return -rte_errno;
}
@@ -224,10 +220,10 @@ mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind,
(1 << MLX5_REGEX_WQE_LOG_NUM(priv->has_umr, log_desc));
else
qp->nb_obj = 1;
- qp->sqs = rte_malloc(NULL,
- qp->nb_obj * sizeof(struct mlx5_regex_sq), 64);
- if (!qp->sqs) {
- DRV_LOG(ERR, "Can't allocate sq array memory.");
+ qp->qps = rte_malloc(NULL,
+ qp->nb_obj * sizeof(struct mlx5_regex_inner_qp), 64);
+ if (!qp->qps) {
+ DRV_LOG(ERR, "Can't allocate qp array memory.");
rte_errno = ENOMEM;
return -rte_errno;
}
@@ -238,9 +234,9 @@ mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind,
goto err_cq;
}
for (i = 0; i < qp->nb_obj; i++) {
- ret = regex_ctrl_create_sq(priv, qp, i, log_desc);
+ ret = regex_ctrl_create_inner_qp(priv, qp, i, log_desc);
if (ret) {
- DRV_LOG(ERR, "Can't create sq.");
+ DRV_LOG(ERR, "Can't create qp object.");
goto err_btree;
}
nb_sq_config++;
@@ -266,9 +262,9 @@ mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind,
mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);
err_btree:
for (i = 0; i < nb_sq_config; i++)
- regex_ctrl_destroy_sq(qp, i);
+ regex_ctrl_destroy_inner_qp(qp, i);
regex_ctrl_destroy_cq(&qp->cq);
err_cq:
- rte_free(qp->sqs);
+ rte_free(qp->qps);
return ret;
}
--
2.27.0
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