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* [PATCH 1/4] common/cnxk: use aggregate level rr prio from mbox
@ 2022-03-28  6:47 Nithin Dabilpuram
  2022-03-28  6:47 ` [PATCH 2/4] net/cnxk: support loopback mode on AF VF's Nithin Dabilpuram
                   ` (2 more replies)
  0 siblings, 3 replies; 5+ messages in thread
From: Nithin Dabilpuram @ 2022-03-28  6:47 UTC (permalink / raw)
  To: jerinj, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao; +Cc: dev

Use aggregate level Round Robin Priority from mbox response instead of
fixing it to single macro. This is useful when kernel AF driver
changes the constant.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/common/cnxk/roc_nix_priv.h     | 5 +++--
 drivers/common/cnxk/roc_nix_tm.c       | 3 ++-
 drivers/common/cnxk/roc_nix_tm_utils.c | 8 ++++----
 3 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h
index 9b9ffae..cc69d71 100644
--- a/drivers/common/cnxk/roc_nix_priv.h
+++ b/drivers/common/cnxk/roc_nix_priv.h
@@ -181,6 +181,7 @@ struct nix {
 	uint16_t tm_root_lvl;
 	uint16_t tm_flags;
 	uint16_t tm_link_cfg_lvl;
+	uint8_t tm_aggr_lvl_rr_prio;
 	uint16_t contig_rsvd[NIX_TXSCH_LVL_CNT];
 	uint16_t discontig_rsvd[NIX_TXSCH_LVL_CNT];
 	uint64_t tm_markfmt_en;
@@ -284,7 +285,6 @@ void nix_unregister_irqs(struct nix *nix);
 
 /* Default TL1 priority and Quantum from AF */
 #define NIX_TM_TL1_DFLT_RR_QTM	((1 << 24) - 1)
-#define NIX_TM_TL1_DFLT_RR_PRIO 1
 
 struct nix_tm_shaper_data {
 	uint64_t burst_exponent;
@@ -432,7 +432,8 @@ bool nix_tm_child_res_valid(struct nix_tm_node_list *list,
 			    struct nix_tm_node *parent);
 uint16_t nix_tm_resource_estimate(struct nix *nix, uint16_t *schq_contig,
 				  uint16_t *schq, enum roc_nix_tm_tree tree);
-uint8_t nix_tm_tl1_default_prep(uint32_t schq, volatile uint64_t *reg,
+uint8_t nix_tm_tl1_default_prep(struct nix *nix, uint32_t schq,
+				volatile uint64_t *reg,
 				volatile uint64_t *regval);
 uint8_t nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node,
 				 volatile uint64_t *reg,
diff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c
index 5b70c7b..84815d0 100644
--- a/drivers/common/cnxk/roc_nix_tm.c
+++ b/drivers/common/cnxk/roc_nix_tm.c
@@ -55,7 +55,7 @@ nix_tm_node_reg_conf(struct nix *nix, struct nix_tm_node *node)
 		req = mbox_alloc_msg_nix_txschq_cfg(mbox);
 		req->lvl = NIX_TXSCH_LVL_TL1;
 
-		k = nix_tm_tl1_default_prep(node->parent_hw_id, req->reg,
+		k = nix_tm_tl1_default_prep(nix, node->parent_hw_id, req->reg,
 					    req->regval);
 		req->num_regs = k;
 		rc = mbox_process(mbox);
@@ -1281,6 +1281,7 @@ nix_tm_alloc_txschq(struct nix *nix, enum roc_nix_tm_tree tree)
 	} while (pend);
 
 	nix->tm_link_cfg_lvl = rsp->link_cfg_lvl;
+	nix->tm_aggr_lvl_rr_prio = rsp->aggr_lvl_rr_prio;
 	return 0;
 alloc_err:
 	for (i = 0; i < NIX_TXSCH_LVL_CNT; i++) {
diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c
index bcdf990..b9b605f 100644
--- a/drivers/common/cnxk/roc_nix_tm_utils.c
+++ b/drivers/common/cnxk/roc_nix_tm_utils.c
@@ -478,7 +478,7 @@ nix_tm_child_res_valid(struct nix_tm_node_list *list,
 }
 
 uint8_t
-nix_tm_tl1_default_prep(uint32_t schq, volatile uint64_t *reg,
+nix_tm_tl1_default_prep(struct nix *nix, uint32_t schq, volatile uint64_t *reg,
 			volatile uint64_t *regval)
 {
 	uint8_t k = 0;
@@ -496,7 +496,7 @@ nix_tm_tl1_default_prep(uint32_t schq, volatile uint64_t *reg,
 	k++;
 
 	reg[k] = NIX_AF_TL1X_TOPOLOGY(schq);
-	regval[k] = (NIX_TM_TL1_DFLT_RR_PRIO << 1);
+	regval[k] = (nix->tm_aggr_lvl_rr_prio << 1);
 	k++;
 
 	reg[k] = NIX_AF_TL1X_CIR(schq);
@@ -540,7 +540,7 @@ nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node,
 	 * Static Priority is disabled
 	 */
 	if (hw_lvl == NIX_TXSCH_LVL_TL1 && nix->tm_flags & NIX_TM_TL1_NO_SP) {
-		rr_prio = NIX_TM_TL1_DFLT_RR_PRIO;
+		rr_prio = nix->tm_aggr_lvl_rr_prio;
 		child = 0;
 	}
 
@@ -662,7 +662,7 @@ nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node *node,
 	 */
 	if (hw_lvl == NIX_TXSCH_LVL_TL2 &&
 	    (!nix_tm_have_tl1_access(nix) || nix->tm_flags & NIX_TM_TL1_NO_SP))
-		strict_prio = NIX_TM_TL1_DFLT_RR_PRIO;
+		strict_prio = nix->tm_aggr_lvl_rr_prio;
 
 	plt_tm_dbg("Schedule config node %s(%u) lvl %u id %u, "
 		   "prio 0x%" PRIx64 ", rr_quantum/rr_wt 0x%" PRIx64 " (%p)",
-- 
2.8.4


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 2/4] net/cnxk: support loopback mode on AF VF's
  2022-03-28  6:47 [PATCH 1/4] common/cnxk: use aggregate level rr prio from mbox Nithin Dabilpuram
@ 2022-03-28  6:47 ` Nithin Dabilpuram
  2022-03-28  6:47 ` [PATCH 3/4] net/cnxk: update LBK ethdev link info Nithin Dabilpuram
  2022-03-28  6:47 ` [PATCH 4/4] net/cnxk: add barrier after meta batch free in scalar Nithin Dabilpuram
  2 siblings, 0 replies; 5+ messages in thread
From: Nithin Dabilpuram @ 2022-03-28  6:47 UTC (permalink / raw)
  To: jerinj, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao; +Cc: dev

Support internal loopback mode on AF VF's using RoC by setting
Tx channel same as Rx channel.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/net/cnxk/cnxk_ethdev.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index 1fa4131..7f8479a 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -1116,6 +1116,9 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev)
 	nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
 	nb_txq = RTE_MAX(data->nb_tx_queues, 1);
 
+	if (roc_nix_is_lbk(nix))
+		nix->enable_loop = eth_dev->data->dev_conf.lpbk_mode;
+
 	/* Alloc a nix lf */
 	rc = roc_nix_lf_alloc(nix, nb_rxq, nb_txq, rx_cfg);
 	if (rc) {
@@ -1239,6 +1242,9 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev)
 		}
 	}
 
+	if (roc_nix_is_lbk(nix))
+		goto skip_lbk_setup;
+
 	/* Configure loop back mode */
 	rc = roc_nix_mac_loopback_enable(nix,
 					 eth_dev->data->dev_conf.lpbk_mode);
@@ -1247,6 +1253,7 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev)
 		goto cq_fini;
 	}
 
+skip_lbk_setup:
 	/* Setup Inline security support */
 	rc = nix_security_setup(dev);
 	if (rc)
-- 
2.8.4


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 3/4] net/cnxk: update LBK ethdev link info
  2022-03-28  6:47 [PATCH 1/4] common/cnxk: use aggregate level rr prio from mbox Nithin Dabilpuram
  2022-03-28  6:47 ` [PATCH 2/4] net/cnxk: support loopback mode on AF VF's Nithin Dabilpuram
@ 2022-03-28  6:47 ` Nithin Dabilpuram
  2022-03-28  6:47 ` [PATCH 4/4] net/cnxk: add barrier after meta batch free in scalar Nithin Dabilpuram
  2 siblings, 0 replies; 5+ messages in thread
From: Nithin Dabilpuram @ 2022-03-28  6:47 UTC (permalink / raw)
  To: jerinj, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao; +Cc: dev

Update link info of LBK ethdev i.e AF's VF's as always up
and 100G. This is because there is no phy for the LBK interfaces
and we won't get a link update notification for the same.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/net/cnxk/cnxk_link.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/net/cnxk/cnxk_link.c b/drivers/net/cnxk/cnxk_link.c
index f10a502..b1d59e3 100644
--- a/drivers/net/cnxk/cnxk_link.c
+++ b/drivers/net/cnxk/cnxk_link.c
@@ -12,6 +12,17 @@ cnxk_nix_toggle_flag_link_cfg(struct cnxk_eth_dev *dev, bool set)
 	else
 		dev->flags &= ~CNXK_LINK_CFG_IN_PROGRESS_F;
 
+	/* Update link info for LBK */
+	if (!set && roc_nix_is_lbk(&dev->nix)) {
+		struct rte_eth_link link;
+
+		link.link_status = RTE_ETH_LINK_UP;
+		link.link_speed = RTE_ETH_SPEED_NUM_100G;
+		link.link_autoneg = RTE_ETH_LINK_FIXED;
+		link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
+		rte_eth_linkstatus_set(dev->eth_dev, &link);
+	}
+
 	rte_wmb();
 }
 
-- 
2.8.4


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 4/4] net/cnxk: add barrier after meta batch free in scalar
  2022-03-28  6:47 [PATCH 1/4] common/cnxk: use aggregate level rr prio from mbox Nithin Dabilpuram
  2022-03-28  6:47 ` [PATCH 2/4] net/cnxk: support loopback mode on AF VF's Nithin Dabilpuram
  2022-03-28  6:47 ` [PATCH 3/4] net/cnxk: update LBK ethdev link info Nithin Dabilpuram
@ 2022-03-28  6:47 ` Nithin Dabilpuram
  2 siblings, 0 replies; 5+ messages in thread
From: Nithin Dabilpuram @ 2022-03-28  6:47 UTC (permalink / raw)
  To: jerinj, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao
  Cc: dev, stable

Add barrier after meta batch free in scalar routine when
lmt lines are exactly full to make sure that next LMT line user
in Tx only starts writing the lines only when previous stoerl's
are complete.

Fixes: 4382a7ccf781 ("net/cnxk: support Rx security offload on cn10k")
Cc: stable@dpdk.org

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/net/cnxk/cn10k_rx.h | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h
index e4f5a55..94c1f1e 100644
--- a/drivers/net/cnxk/cn10k_rx.h
+++ b/drivers/net/cnxk/cn10k_rx.h
@@ -1007,10 +1007,11 @@ cn10k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts,
 	plt_write64((wdata | nb_pkts), rxq->cq_door);
 
 	/* Free remaining meta buffers if any */
-	if (flags & NIX_RX_OFFLOAD_SECURITY_F && loff) {
+	if (flags & NIX_RX_OFFLOAD_SECURITY_F && loff)
 		nix_sec_flush_meta(laddr, lmt_id + lnum, loff, aura_handle);
-		plt_io_wmb();
-	}
+
+	if (flags & NIX_RX_OFFLOAD_SECURITY_F)
+		rte_io_wmb();
 
 	return nb_pkts;
 }
-- 
2.8.4


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 4/4] net/cnxk: add barrier after meta batch free in scalar
  2022-03-28  5:47 [PATCH 1/4] common/cnxk: use aggregate level rr prio from mbox Nithin Dabilpuram
@ 2022-03-28  5:47 ` Nithin Dabilpuram
  0 siblings, 0 replies; 5+ messages in thread
From: Nithin Dabilpuram @ 2022-03-28  5:47 UTC (permalink / raw)
  To: jerinj, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao
  Cc: dev, stable

Add barrier after meta batch free in scalar routine when
lmt lines are exactly full to make sure that next LMT line user
in Tx only starts writing the lines only when previous stoerl's
are complete.

Fixes: 4382a7ccf781 ("net/cnxk: support Rx security offload on cn10k")
Cc: stable@dpdk.org

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/net/cnxk/cn10k_rx.h | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h
index e4f5a55..94c1f1e 100644
--- a/drivers/net/cnxk/cn10k_rx.h
+++ b/drivers/net/cnxk/cn10k_rx.h
@@ -1007,10 +1007,11 @@ cn10k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts,
 	plt_write64((wdata | nb_pkts), rxq->cq_door);
 
 	/* Free remaining meta buffers if any */
-	if (flags & NIX_RX_OFFLOAD_SECURITY_F && loff) {
+	if (flags & NIX_RX_OFFLOAD_SECURITY_F && loff)
 		nix_sec_flush_meta(laddr, lmt_id + lnum, loff, aura_handle);
-		plt_io_wmb();
-	}
+
+	if (flags & NIX_RX_OFFLOAD_SECURITY_F)
+		rte_io_wmb();
 
 	return nb_pkts;
 }
-- 
2.8.4


^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2022-03-28  6:48 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2022-03-28  6:47 ` [PATCH 3/4] net/cnxk: update LBK ethdev link info Nithin Dabilpuram
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