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From: Nithin Dabilpuram <ndabilpuram@marvell.com>
To: <jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>,
	"Kiran Kumar K" <kirankumark@marvell.com>,
	Sunil Kumar Kori <skori@marvell.com>,
	Satha Rao <skoteshwar@marvell.com>
Cc: <dev@dpdk.org>
Subject: [PATCH v2 05/28] common/cnxk: fix SQ flush sequence
Date: Fri, 22 Apr 2022 16:16:46 +0530	[thread overview]
Message-ID: <20220422104709.20722-5-ndabilpuram@marvell.com> (raw)
In-Reply-To: <20220422104709.20722-1-ndabilpuram@marvell.com>

From: Satha Rao <skoteshwar@marvell.com>

Fix SQ flush sequence to issue NIX RX SW Sync after SMQ flush.
This sync ensures that all the packets that were inflight are
flushed out of memory.

This patch also fixes NULL return issues reported by
static analysis tool in Traffic Manager and sync's mbox
to that of Kernel version.

Fixes: 05d727e8b14a ("common/cnxk: support NIX traffic management")
Fixes: 0b7e667ee303 ("common/cnxk: enable packet marking")

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---
 drivers/common/cnxk/roc_mbox.h        | 35 +++++++++++++++++++++++++++++++++--
 drivers/common/cnxk/roc_nix_tm.c      |  7 +++++++
 drivers/common/cnxk/roc_nix_tm_mark.c |  9 +++++++++
 3 files changed, 49 insertions(+), 2 deletions(-)

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index b608f58..2c30f19 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -116,7 +116,7 @@ struct mbox_msghdr {
 	  msg_rsp)                                                             \
 	M(SSO_GRP_GET_PRIORITY, 0x606, sso_grp_get_priority, sso_info_req,     \
 	  sso_grp_priority)                                                    \
-	M(SSO_WS_CACHE_INV, 0x607, sso_ws_cache_inv, msg_req, msg_rsp)         \
+	M(SSO_WS_CACHE_INV, 0x607, sso_ws_cache_inv, ssow_lf_inv_req, msg_rsp) \
 	M(SSO_GRP_QOS_CONFIG, 0x608, sso_grp_qos_config, sso_grp_qos_cfg,      \
 	  msg_rsp)                                                             \
 	M(SSO_GRP_GET_STATS, 0x609, sso_grp_get_stats, sso_info_req,           \
@@ -125,6 +125,9 @@ struct mbox_msghdr {
 	  sso_hws_stats)                                                       \
 	M(SSO_HW_RELEASE_XAQ, 0x611, sso_hw_release_xaq_aura,                  \
 	  sso_hw_xaq_release, msg_rsp)                                         \
+	M(SSO_CONFIG_LSW, 0x612, ssow_config_lsw, ssow_config_lsw, msg_rsp)    \
+	M(SSO_HWS_CHNG_MSHIP, 0x613, ssow_chng_mship, ssow_chng_mship,         \
+	  msg_rsp)                                                             \
 	/* TIM mbox IDs (range 0x800 - 0x9FF) */                               \
 	M(TIM_LF_ALLOC, 0x800, tim_lf_alloc, tim_lf_alloc_req,                 \
 	  tim_lf_alloc_rsp)                                                    \
@@ -259,7 +262,8 @@ struct mbox_msghdr {
 	M(NIX_CPT_BP_ENABLE, 0x8020, nix_cpt_bp_enable, nix_bp_cfg_req,        \
 	  nix_bp_cfg_rsp)                                                      \
 	M(NIX_CPT_BP_DISABLE, 0x8021, nix_cpt_bp_disable, nix_bp_cfg_req,      \
-	  msg_rsp)
+	  msg_rsp)                                                             \
+	M(NIX_RX_SW_SYNC, 0x8022, nix_rx_sw_sync, msg_req, msg_rsp)
 
 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
 #define MBOX_UP_CGX_MESSAGES                                                   \
@@ -1268,6 +1272,33 @@ struct ssow_lf_free_req {
 	uint16_t __io hws;
 };
 
+#define SSOW_INVAL_SELECTIVE_VER 0x1000
+struct ssow_lf_inv_req {
+	struct mbox_msghdr hdr;
+	uint16_t nb_hws;		 /* Number of HWS to invalidate*/
+	uint16_t hws[MAX_RVU_BLKLF_CNT]; /* Array of HWS */
+};
+
+struct ssow_config_lsw {
+	struct mbox_msghdr hdr;
+#define SSOW_LSW_DIS	 0
+#define SSOW_LSW_GW_WAIT 1
+#define SSOW_LSW_GW_IMM	 2
+	uint8_t __io lsw_mode;
+#define SSOW_WQE_REL_LSW_WAIT 0
+#define SSOW_WQE_REL_IMM      1
+	uint8_t __io wqe_release;
+};
+
+struct ssow_chng_mship {
+	struct mbox_msghdr hdr;
+	uint8_t __io set;	 /* Membership set to modify. */
+	uint8_t __io enable;	 /* Enable/Disable the hwgrps. */
+	uint8_t __io hws;	 /* HWS to modify. */
+	uint16_t __io nb_hwgrps; /* Number of hwgrps in the array */
+	uint16_t __io hwgrps[MAX_RVU_BLKLF_CNT]; /* Array of hwgrps. */
+};
+
 struct sso_hw_setconfig {
 	struct mbox_msghdr hdr;
 	uint32_t __io npa_aura_id;
diff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c
index 5b70c7b..42d3abd 100644
--- a/drivers/common/cnxk/roc_nix_tm.c
+++ b/drivers/common/cnxk/roc_nix_tm.c
@@ -590,6 +590,7 @@ nix_tm_sq_flush_pre(struct roc_nix_sq *sq)
 	struct nix_tm_node *node, *sibling;
 	struct nix_tm_node_list *list;
 	enum roc_nix_tm_tree tree;
+	struct msg_req *req;
 	struct mbox *mbox;
 	struct nix *nix;
 	uint16_t qid;
@@ -679,6 +680,12 @@ nix_tm_sq_flush_pre(struct roc_nix_sq *sq)
 			rc);
 		goto cleanup;
 	}
+
+	req = mbox_alloc_msg_nix_rx_sw_sync(mbox);
+	if (!req)
+		return -ENOSPC;
+
+	rc = mbox_process(mbox);
 cleanup:
 	/* Restore cgx state */
 	if (!roc_nix->io_enabled) {
diff --git a/drivers/common/cnxk/roc_nix_tm_mark.c b/drivers/common/cnxk/roc_nix_tm_mark.c
index 64cf679..d37292e 100644
--- a/drivers/common/cnxk/roc_nix_tm_mark.c
+++ b/drivers/common/cnxk/roc_nix_tm_mark.c
@@ -110,6 +110,9 @@ nix_tm_update_red_algo(struct nix *nix, bool red_send)
 
 		/* Update txschq config  */
 		req = mbox_alloc_msg_nix_txschq_cfg(mbox);
+		if (req == NULL)
+			return -ENOSPC;
+
 		req->lvl = tm_node->hw_lvl;
 		k = prepare_tm_shaper_red_algo(tm_node, req->reg, req->regval,
 					       req->regval_mask);
@@ -208,6 +211,9 @@ nix_tm_mark_init(struct nix *nix)
 
 	/* Null mark format */
 	req = mbox_alloc_msg_nix_mark_format_cfg(mbox);
+	if (req == NULL)
+		return -ENOSPC;
+
 	rc = mbox_process_msg(mbox, (void *)&rsp);
 	if (rc) {
 		plt_err("TM failed to alloc null mark format, rc=%d", rc);
@@ -220,6 +226,9 @@ nix_tm_mark_init(struct nix *nix)
 	for (i = 0; i < ROC_NIX_TM_MARK_MAX; i++) {
 		for (j = 0; j < ROC_NIX_TM_MARK_COLOR_MAX; j++) {
 			req = mbox_alloc_msg_nix_mark_format_cfg(mbox);
+			if (req == NULL)
+				return -ENOSPC;
+
 			req->offset = mark_off[i];
 
 			switch (j) {
-- 
2.8.4


  parent reply	other threads:[~2022-04-22 10:47 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-22 10:46 [PATCH v2 01/28] common/cnxk: add multi channel support for SDP send queues Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 02/28] net/cnxk: add receive channel backpressure for SDP Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 03/28] common/cnxk: add new pkind for CPT when ts is enabled Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 04/28] common/cnxk: support to configure the ts pkind in CPT Nithin Dabilpuram
2022-04-26 10:12   ` Ray Kinsella
2022-04-22 10:46 ` Nithin Dabilpuram [this message]
2022-04-22 10:46 ` [PATCH v2 06/28] common/cnxk: skip probing SoC environment for CN9k Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 07/28] common/cnxk: fix issues in soft expiry disable path Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 08/28] common/cnxk: convert warning to debug print Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 09/28] common/cnxk: use aggregate level rr prio from mbox Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 10/28] net/cnxk: support loopback mode on AF VF's Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 11/28] net/cnxk: update LBK ethdev link info Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 12/28] net/cnxk: add barrier after meta batch free in scalar Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 13/28] net/cnxk: disable default inner chksum for outb inline Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 14/28] net/cnxk: fix roundup size with transport mode Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 15/28] net/cnxk: update inline device in ethdev telemetry Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 16/28] net/cnxk: change env for debug IV Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 17/28] net/cnxk: reset offload flag if reassembly is disabled Nithin Dabilpuram
2022-04-22 10:46 ` [PATCH v2 18/28] net/cnxk: support decrement TTL for inline IPsec Nithin Dabilpuram
2022-04-22 10:47 ` [PATCH v2 19/28] net/cnxk: optimize Rx fast path for security pkts Nithin Dabilpuram
2022-04-22 10:47 ` [PATCH v2 20/28] net/cnxk: update olflags with L3/L4 csum offload Nithin Dabilpuram
2022-04-22 10:47 ` [PATCH v2 21/28] net/cnxk: add capabilities for IPsec crypto algos Nithin Dabilpuram
2022-04-22 10:47 ` [PATCH v2 22/28] net/cnxk: add capabilities for IPsec options Nithin Dabilpuram
2022-04-22 10:47 ` [PATCH v2 23/28] net/cnxk: support security stats Nithin Dabilpuram
2022-04-22 10:47 ` [PATCH v2 24/28] net/cnxk: add support for flow control for outbound inline Nithin Dabilpuram
2022-04-22 10:47 ` [PATCH v2 25/28] net/cnxk: perform early MTU setup for eventmode Nithin Dabilpuram
2022-04-22 10:47 ` [PATCH v2 26/28] common/cnxk: allow lesser inline inbound sa sizes Nithin Dabilpuram
2022-04-22 10:47 ` [PATCH v2 27/28] net/cnxk: setup variable inline inbound SA Nithin Dabilpuram
2022-04-22 10:47 ` [PATCH v2 28/28] net/cnxk: fix multi-seg extraction in vwqe path Nithin Dabilpuram
2022-04-22 10:54   ` Pavan Nikhilesh Bhagavatula
2022-05-03 17:36   ` Jerin Jacob

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