* [PATCH] net/mlx5/hws: support match on ESP item
@ 2023-02-06 9:55 Viacheslav Ovsiienko
2023-02-07 11:40 ` [PATCH v2] " Viacheslav Ovsiienko
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Viacheslav Ovsiienko @ 2023-02-06 9:55 UTC (permalink / raw)
To: dev; +Cc: matan, rasland, orika, Hamdan Igbaria
From: Hamdan Igbaria <hamdani@nvidia.com>
Add the support to match on SPI and sequence
number fields of ESP header.
The match on ESP header in harwdare steering
is supported only if firmware reports the device
supports IPsec offload.
Signed-off-by: Hamdan Igbaria <hamdani@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
drivers/common/mlx5/mlx5_prm.h | 3 ++-
drivers/net/mlx5/hws/mlx5dr_cmd.c | 3 +++
drivers/net/mlx5/hws/mlx5dr_cmd.h | 1 +
drivers/net/mlx5/hws/mlx5dr_definer.c | 38 ++++++++++++++++++++++++++-
drivers/net/mlx5/hws/mlx5dr_definer.h | 2 ++
drivers/net/mlx5/mlx5_flow_hw.c | 1 +
6 files changed, 46 insertions(+), 2 deletions(-)
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 9294f65e24..0ee4b575d4 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -1695,7 +1695,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 reserved_at_460[0x8];
u8 aes_xts[0x1];
u8 crypto[0x1];
- u8 reserved_at_46a[0x6];
+ u8 ipsec_offload[0x1];
+ u8 reserved_at_46b[0x5];
u8 max_num_eqs[0x10];
u8 reserved_at_480[0x3];
u8 log_max_l2_table[0x5];
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c
index 32378673cf..c60da381b2 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.c
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c
@@ -850,6 +850,9 @@ int mlx5dr_cmd_query_caps(struct ibv_context *ctx,
caps->sq_ts_format = MLX5_GET(query_hca_cap_out, out,
capability.cmd_hca_cap.sq_ts_format);
+ caps->ipsec_offload = MLX5_GET(query_hca_cap_out, out,
+ capability.cmd_hca_cap.ipsec_offload);
+
MLX5_SET(query_hca_cap_in, in, op_mod,
MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |
MLX5_HCA_CAP_OPMOD_GET_CUR);
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h b/drivers/net/mlx5/hws/mlx5dr_cmd.h
index 468557ba16..af779e4bcd 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.h
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h
@@ -188,6 +188,7 @@ struct mlx5dr_cmd_query_caps {
bool cross_vhca_resources;
uint32_t shared_vhca_id;
char fw_ver[64];
+ bool ipsec_offload;
};
int mlx5dr_cmd_destroy_obj(struct mlx5dr_devx_obj *devx_obj);
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index 6b98eb8c96..ab65409629 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -162,7 +162,9 @@ struct mlx5dr_definer_conv_data {
X(SET_BE32, gre_opt_key, v->key.key, rte_flow_item_gre_opt) \
X(SET_BE32, gre_opt_seq, v->sequence.sequence, rte_flow_item_gre_opt) \
X(SET_BE16, gre_opt_checksum, v->checksum_rsvd.checksum, rte_flow_item_gre_opt) \
- X(SET, meter_color, rte_col_2_mlx5_col(v->color), rte_flow_item_meter_color)
+ X(SET, meter_color, rte_col_2_mlx5_col(v->color), rte_flow_item_meter_color) \
+ X(SET_BE32, ipsec_spi, v->hdr.spi, rte_flow_item_esp) \
+ X(SET_BE32, ipsec_sequence_number, v->hdr.seq, rte_flow_item_esp)
/* Item set function format */
#define X(set_type, func_name, value, item_type) \
@@ -1465,6 +1467,36 @@ mlx5dr_definer_conv_item_meter_color(struct mlx5dr_definer_conv_data *cd,
return 0;
}
+static int
+mlx5dr_definer_conv_item_esp(struct mlx5dr_definer_conv_data *cd,
+ struct rte_flow_item *item,
+ int item_idx)
+{
+ const struct rte_flow_item_esp *m = item->mask;
+ struct mlx5dr_definer_fc *fc;
+
+ if (!cd->caps->ipsec_offload) {
+ rte_errno = ENOTSUP;
+ return rte_errno;
+ }
+
+ if (!m)
+ return 0;
+ if (m->hdr.spi) {
+ fc = &cd->fc[MLX5DR_DEFINER_FNAME_ESP_SPI];
+ fc->item_idx = item_idx;
+ fc->tag_set = &mlx5dr_definer_ipsec_spi_set;
+ DR_CALC_SET_HDR(fc, ipsec, spi);
+ }
+ if (m->hdr.seq) {
+ fc = &cd->fc[MLX5DR_DEFINER_FNAME_ESP_SEQUENCE_NUMBER];
+ fc->item_idx = item_idx;
+ fc->tag_set = &mlx5dr_definer_ipsec_sequence_number_set;
+ DR_CALC_SET_HDR(fc, ipsec, sequence_number);
+ }
+ return 0;
+}
+
static int
mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,
struct mlx5dr_match_template *mt,
@@ -1581,6 +1613,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,
ret = mlx5dr_definer_conv_item_meter_color(&cd, items, i);
item_flags |= MLX5_FLOW_ITEM_METER_COLOR;
break;
+ case RTE_FLOW_ITEM_TYPE_ESP:
+ ret = mlx5dr_definer_conv_item_esp(&cd, items, i);
+ item_flags |= MLX5_FLOW_ITEM_ESP;
+ break;
default:
DR_LOG(ERR, "Unsupported item type %d", items->type);
rte_errno = ENOTSUP;
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h
index d52c6b0627..d0ecbe9325 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.h
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h
@@ -106,6 +106,8 @@ enum mlx5dr_definer_fname {
MLX5DR_DEFINER_FNAME_INTEGRITY_I,
MLX5DR_DEFINER_FNAME_ICMP_DW1,
MLX5DR_DEFINER_FNAME_ICMP_DW2,
+ MLX5DR_DEFINER_FNAME_ESP_SPI,
+ MLX5DR_DEFINER_FNAME_ESP_SEQUENCE_NUMBER,
MLX5DR_DEFINER_FNAME_MAX,
};
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 20c71ff7f0..ce9e0219e1 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -4732,6 +4732,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,
case RTE_FLOW_ITEM_TYPE_ICMP:
case RTE_FLOW_ITEM_TYPE_ICMP6:
case RTE_FLOW_ITEM_TYPE_CONNTRACK:
+ case RTE_FLOW_ITEM_TYPE_ESP:
break;
case RTE_FLOW_ITEM_TYPE_INTEGRITY:
/*
--
2.18.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v2] net/mlx5/hws: support match on ESP item
2023-02-06 9:55 [PATCH] net/mlx5/hws: support match on ESP item Viacheslav Ovsiienko
@ 2023-02-07 11:40 ` Viacheslav Ovsiienko
2023-02-07 13:56 ` [PATCH v2] doc: update cross-port indirect shared action Viacheslav Ovsiienko
2023-02-13 13:45 ` [PATCH v3] net/mlx5/hws: support match on ESP item Viacheslav Ovsiienko
2 siblings, 0 replies; 4+ messages in thread
From: Viacheslav Ovsiienko @ 2023-02-07 11:40 UTC (permalink / raw)
To: dev; +Cc: matan, rasland, orika, Hamdan Igbaria
From: Hamdan Igbaria <hamdani@nvidia.com>
Add the support to match on SPI and sequence
number fields of ESP header.
The match on ESP header in hardware steering
is supported only if firmware reports the device
supports IPsec offload.
Signed-off-by: Hamdan Igbaria <hamdani@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
drivers/common/mlx5/mlx5_prm.h | 3 ++-
drivers/net/mlx5/hws/mlx5dr_cmd.c | 3 +++
drivers/net/mlx5/hws/mlx5dr_cmd.h | 1 +
drivers/net/mlx5/hws/mlx5dr_definer.c | 38 ++++++++++++++++++++++++++-
drivers/net/mlx5/hws/mlx5dr_definer.h | 2 ++
drivers/net/mlx5/mlx5_flow_hw.c | 1 +
6 files changed, 46 insertions(+), 2 deletions(-)
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 9294f65e24..0ee4b575d4 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -1695,7 +1695,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 reserved_at_460[0x8];
u8 aes_xts[0x1];
u8 crypto[0x1];
- u8 reserved_at_46a[0x6];
+ u8 ipsec_offload[0x1];
+ u8 reserved_at_46b[0x5];
u8 max_num_eqs[0x10];
u8 reserved_at_480[0x3];
u8 log_max_l2_table[0x5];
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c
index 32378673cf..c60da381b2 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.c
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c
@@ -850,6 +850,9 @@ int mlx5dr_cmd_query_caps(struct ibv_context *ctx,
caps->sq_ts_format = MLX5_GET(query_hca_cap_out, out,
capability.cmd_hca_cap.sq_ts_format);
+ caps->ipsec_offload = MLX5_GET(query_hca_cap_out, out,
+ capability.cmd_hca_cap.ipsec_offload);
+
MLX5_SET(query_hca_cap_in, in, op_mod,
MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |
MLX5_HCA_CAP_OPMOD_GET_CUR);
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h b/drivers/net/mlx5/hws/mlx5dr_cmd.h
index 468557ba16..af779e4bcd 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.h
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h
@@ -188,6 +188,7 @@ struct mlx5dr_cmd_query_caps {
bool cross_vhca_resources;
uint32_t shared_vhca_id;
char fw_ver[64];
+ bool ipsec_offload;
};
int mlx5dr_cmd_destroy_obj(struct mlx5dr_devx_obj *devx_obj);
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index 6b98eb8c96..ab65409629 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -162,7 +162,9 @@ struct mlx5dr_definer_conv_data {
X(SET_BE32, gre_opt_key, v->key.key, rte_flow_item_gre_opt) \
X(SET_BE32, gre_opt_seq, v->sequence.sequence, rte_flow_item_gre_opt) \
X(SET_BE16, gre_opt_checksum, v->checksum_rsvd.checksum, rte_flow_item_gre_opt) \
- X(SET, meter_color, rte_col_2_mlx5_col(v->color), rte_flow_item_meter_color)
+ X(SET, meter_color, rte_col_2_mlx5_col(v->color), rte_flow_item_meter_color) \
+ X(SET_BE32, ipsec_spi, v->hdr.spi, rte_flow_item_esp) \
+ X(SET_BE32, ipsec_sequence_number, v->hdr.seq, rte_flow_item_esp)
/* Item set function format */
#define X(set_type, func_name, value, item_type) \
@@ -1465,6 +1467,36 @@ mlx5dr_definer_conv_item_meter_color(struct mlx5dr_definer_conv_data *cd,
return 0;
}
+static int
+mlx5dr_definer_conv_item_esp(struct mlx5dr_definer_conv_data *cd,
+ struct rte_flow_item *item,
+ int item_idx)
+{
+ const struct rte_flow_item_esp *m = item->mask;
+ struct mlx5dr_definer_fc *fc;
+
+ if (!cd->caps->ipsec_offload) {
+ rte_errno = ENOTSUP;
+ return rte_errno;
+ }
+
+ if (!m)
+ return 0;
+ if (m->hdr.spi) {
+ fc = &cd->fc[MLX5DR_DEFINER_FNAME_ESP_SPI];
+ fc->item_idx = item_idx;
+ fc->tag_set = &mlx5dr_definer_ipsec_spi_set;
+ DR_CALC_SET_HDR(fc, ipsec, spi);
+ }
+ if (m->hdr.seq) {
+ fc = &cd->fc[MLX5DR_DEFINER_FNAME_ESP_SEQUENCE_NUMBER];
+ fc->item_idx = item_idx;
+ fc->tag_set = &mlx5dr_definer_ipsec_sequence_number_set;
+ DR_CALC_SET_HDR(fc, ipsec, sequence_number);
+ }
+ return 0;
+}
+
static int
mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,
struct mlx5dr_match_template *mt,
@@ -1581,6 +1613,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,
ret = mlx5dr_definer_conv_item_meter_color(&cd, items, i);
item_flags |= MLX5_FLOW_ITEM_METER_COLOR;
break;
+ case RTE_FLOW_ITEM_TYPE_ESP:
+ ret = mlx5dr_definer_conv_item_esp(&cd, items, i);
+ item_flags |= MLX5_FLOW_ITEM_ESP;
+ break;
default:
DR_LOG(ERR, "Unsupported item type %d", items->type);
rte_errno = ENOTSUP;
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h
index d52c6b0627..d0ecbe9325 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.h
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h
@@ -106,6 +106,8 @@ enum mlx5dr_definer_fname {
MLX5DR_DEFINER_FNAME_INTEGRITY_I,
MLX5DR_DEFINER_FNAME_ICMP_DW1,
MLX5DR_DEFINER_FNAME_ICMP_DW2,
+ MLX5DR_DEFINER_FNAME_ESP_SPI,
+ MLX5DR_DEFINER_FNAME_ESP_SEQUENCE_NUMBER,
MLX5DR_DEFINER_FNAME_MAX,
};
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 20c71ff7f0..ce9e0219e1 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -4732,6 +4732,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,
case RTE_FLOW_ITEM_TYPE_ICMP:
case RTE_FLOW_ITEM_TYPE_ICMP6:
case RTE_FLOW_ITEM_TYPE_CONNTRACK:
+ case RTE_FLOW_ITEM_TYPE_ESP:
break;
case RTE_FLOW_ITEM_TYPE_INTEGRITY:
/*
--
2.18.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v2] doc: update cross-port indirect shared action
2023-02-06 9:55 [PATCH] net/mlx5/hws: support match on ESP item Viacheslav Ovsiienko
2023-02-07 11:40 ` [PATCH v2] " Viacheslav Ovsiienko
@ 2023-02-07 13:56 ` Viacheslav Ovsiienko
2023-02-13 13:45 ` [PATCH v3] net/mlx5/hws: support match on ESP item Viacheslav Ovsiienko
2 siblings, 0 replies; 4+ messages in thread
From: Viacheslav Ovsiienko @ 2023-02-07 13:56 UTC (permalink / raw)
To: dev; +Cc: matan, rasland, orika
The patch updates the Release Notes and documentation
for the indirect RTE Flow actions as shared ones between
ports on the same physical NIC.
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
doc/guides/rel_notes/release_23_03.rst | 6 ++++++
doc/guides/testpmd_app_ug/testpmd_funcs.rst | 4 +++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/doc/guides/rel_notes/release_23_03.rst b/doc/guides/rel_notes/release_23_03.rst
index c15f6fbb9f..eb6643bc66 100644
--- a/doc/guides/rel_notes/release_23_03.rst
+++ b/doc/guides/rel_notes/release_23_03.rst
@@ -55,6 +55,12 @@ New Features
Also, make sure to start the actual text at the margin.
=======================================================
+* **Added cross-port indirect action in asynchronous Flow API.**
+
+ * Added ``RTE_FLOW_PORT_FLAG_SHARE_INDIRECT`` flag option to
+ ``rte_flow_configure``.
+ * Added ``host_port_id`` to ``rte_flow_port_attr`` structure.
+
* **Updated Intel QuickAssist Technology (QAT) crypto driver.**
* Added support for SHA3 224/256/384/512 plain hash in QAT GEN 3.
diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
index 0037506a79..cf6c214197 100644
--- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
+++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
@@ -3047,7 +3047,9 @@ for asynchronous flow creation/destruction operations. It is bound to
[queues_number {number}] [queues_size {size}]
[counters_number {number}]
[aging_counters_number {number}]
- [meters_number {number}] [flags {number}]
+ [host_port {number}]
+ [meters_number {number}]
+ [flags {number}]
If successful, it will show::
--
2.18.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v3] net/mlx5/hws: support match on ESP item
2023-02-06 9:55 [PATCH] net/mlx5/hws: support match on ESP item Viacheslav Ovsiienko
2023-02-07 11:40 ` [PATCH v2] " Viacheslav Ovsiienko
2023-02-07 13:56 ` [PATCH v2] doc: update cross-port indirect shared action Viacheslav Ovsiienko
@ 2023-02-13 13:45 ` Viacheslav Ovsiienko
2 siblings, 0 replies; 4+ messages in thread
From: Viacheslav Ovsiienko @ 2023-02-13 13:45 UTC (permalink / raw)
To: dev; +Cc: matan, rasland, orika, Hamdan Igbaria
From: Hamdan Igbaria <hamdani@nvidia.com>
Add the support to match on SPI and sequence
number fields of ESP header.
The match on ESP header in hardware steering
is supported only if firmware reports the device
supports IPsec offload.
Signed-off-by: Hamdan Igbaria <hamdani@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
drivers/common/mlx5/mlx5_prm.h | 3 ++-
drivers/net/mlx5/hws/mlx5dr_cmd.c | 3 +++
drivers/net/mlx5/hws/mlx5dr_cmd.h | 1 +
drivers/net/mlx5/hws/mlx5dr_definer.c | 38 ++++++++++++++++++++++++++-
drivers/net/mlx5/hws/mlx5dr_definer.h | 2 ++
drivers/net/mlx5/mlx5_flow_hw.c | 1 +
6 files changed, 46 insertions(+), 2 deletions(-)
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 243952bf85..ad563908ce 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -1696,7 +1696,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 reserved_at_460[0x8];
u8 aes_xts[0x1];
u8 crypto[0x1];
- u8 reserved_at_46a[0x6];
+ u8 ipsec_offload[0x1];
+ u8 reserved_at_46b[0x5];
u8 max_num_eqs[0x10];
u8 reserved_at_480[0x3];
u8 log_max_l2_table[0x5];
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c
index 3578fe4b69..a444fb4438 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.c
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c
@@ -906,6 +906,9 @@ int mlx5dr_cmd_query_caps(struct ibv_context *ctx,
caps->sq_ts_format = MLX5_GET(query_hca_cap_out, out,
capability.cmd_hca_cap.sq_ts_format);
+ caps->ipsec_offload = MLX5_GET(query_hca_cap_out, out,
+ capability.cmd_hca_cap.ipsec_offload);
+
MLX5_SET(query_hca_cap_in, in, op_mod,
MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |
MLX5_HCA_CAP_OPMOD_GET_CUR);
diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h b/drivers/net/mlx5/hws/mlx5dr_cmd.h
index 0fc65aad49..3f40c085be 100644
--- a/drivers/net/mlx5/hws/mlx5dr_cmd.h
+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h
@@ -202,6 +202,7 @@ struct mlx5dr_cmd_query_caps {
bool cross_vhca_resources;
uint32_t shared_vhca_id;
char fw_ver[64];
+ bool ipsec_offload;
};
int mlx5dr_cmd_destroy_obj(struct mlx5dr_devx_obj *devx_obj);
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index 4849158407..b682d7582d 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -162,7 +162,9 @@ struct mlx5dr_definer_conv_data {
X(SET_BE32, gre_opt_key, v->key.key, rte_flow_item_gre_opt) \
X(SET_BE32, gre_opt_seq, v->sequence.sequence, rte_flow_item_gre_opt) \
X(SET_BE16, gre_opt_checksum, v->checksum_rsvd.checksum, rte_flow_item_gre_opt) \
- X(SET, meter_color, rte_col_2_mlx5_col(v->color), rte_flow_item_meter_color)
+ X(SET, meter_color, rte_col_2_mlx5_col(v->color), rte_flow_item_meter_color) \
+ X(SET_BE32, ipsec_spi, v->hdr.spi, rte_flow_item_esp) \
+ X(SET_BE32, ipsec_sequence_number, v->hdr.seq, rte_flow_item_esp)
/* Item set function format */
#define X(set_type, func_name, value, item_type) \
@@ -1645,6 +1647,36 @@ mlx5dr_definer_check_item_range_supp(struct rte_flow_item *item)
}
}
+static int
+mlx5dr_definer_conv_item_esp(struct mlx5dr_definer_conv_data *cd,
+ struct rte_flow_item *item,
+ int item_idx)
+{
+ const struct rte_flow_item_esp *m = item->mask;
+ struct mlx5dr_definer_fc *fc;
+
+ if (!cd->caps->ipsec_offload) {
+ rte_errno = ENOTSUP;
+ return rte_errno;
+ }
+
+ if (!m)
+ return 0;
+ if (m->hdr.spi) {
+ fc = &cd->fc[MLX5DR_DEFINER_FNAME_ESP_SPI];
+ fc->item_idx = item_idx;
+ fc->tag_set = &mlx5dr_definer_ipsec_spi_set;
+ DR_CALC_SET_HDR(fc, ipsec, spi);
+ }
+ if (m->hdr.seq) {
+ fc = &cd->fc[MLX5DR_DEFINER_FNAME_ESP_SEQUENCE_NUMBER];
+ fc->item_idx = item_idx;
+ fc->tag_set = &mlx5dr_definer_ipsec_sequence_number_set;
+ DR_CALC_SET_HDR(fc, ipsec, sequence_number);
+ }
+ return 0;
+}
+
static int
mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,
struct mlx5dr_match_template *mt,
@@ -1767,6 +1799,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,
ret = mlx5dr_definer_conv_item_meter_color(&cd, items, i);
item_flags |= MLX5_FLOW_ITEM_METER_COLOR;
break;
+ case RTE_FLOW_ITEM_TYPE_ESP:
+ ret = mlx5dr_definer_conv_item_esp(&cd, items, i);
+ item_flags |= MLX5_FLOW_ITEM_ESP;
+ break;
default:
DR_LOG(ERR, "Unsupported item type %d", items->type);
rte_errno = ENOTSUP;
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h
index 464872acd6..d8d6157154 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.h
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h
@@ -112,6 +112,8 @@ enum mlx5dr_definer_fname {
MLX5DR_DEFINER_FNAME_INTEGRITY_I,
MLX5DR_DEFINER_FNAME_ICMP_DW1,
MLX5DR_DEFINER_FNAME_ICMP_DW2,
+ MLX5DR_DEFINER_FNAME_ESP_SPI,
+ MLX5DR_DEFINER_FNAME_ESP_SEQUENCE_NUMBER,
MLX5DR_DEFINER_FNAME_MAX,
};
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index aacde224f2..9cbd3b2693 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -4734,6 +4734,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,
case RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REQUEST:
case RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REPLY:
case RTE_FLOW_ITEM_TYPE_CONNTRACK:
+ case RTE_FLOW_ITEM_TYPE_ESP:
break;
case RTE_FLOW_ITEM_TYPE_INTEGRITY:
/*
--
2.18.1
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-02-13 13:46 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-02-06 9:55 [PATCH] net/mlx5/hws: support match on ESP item Viacheslav Ovsiienko
2023-02-07 11:40 ` [PATCH v2] " Viacheslav Ovsiienko
2023-02-07 13:56 ` [PATCH v2] doc: update cross-port indirect shared action Viacheslav Ovsiienko
2023-02-13 13:45 ` [PATCH v3] net/mlx5/hws: support match on ESP item Viacheslav Ovsiienko
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