[PATCH v2 0/2] doc: update FlexRAN SDK links

[PATCH v2 0/2] doc: update FlexRAN SDK links

[Nicolas Chautru]

v2: rebase typo fixed.

Upstreaming SDK workaround for ACC100 and updating documentation for new
SDK release.

Hernan Vargas (2):
  baseband/acc: support ACC100 deRM corner case SDK
  doc: update FlexRAN SDK links

 doc/guides/bbdevs/turbo_sw.rst        | 53 +++++++++++++-----------
 drivers/baseband/acc/meson.build      | 23 ++++++++++-
 drivers/baseband/acc/rte_acc100_pmd.c | 59 +++++++++++++++++++++++++--
 3 files changed, 107 insertions(+), 28 deletions(-)

-- 
2.34.1

[PATCH v2 1/2] baseband/acc: support ACC100 deRM corner case SDK

[Nicolas Chautru]

From: Hernan Vargas <hernan.vargas@intel.com>

Implement de-ratematch pre-processing for ACC100 SW corner cases.
Some specific 5GUL FEC corner cases may cause unintended back pressure
and in some cases a potential stability issue on the ACC100.
The PMD can detect such code block configuration and issue an info
message to the user.

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
 drivers/baseband/acc/meson.build      | 23 ++++++++++-
 drivers/baseband/acc/rte_acc100_pmd.c | 59 +++++++++++++++++++++++++--
 2 files changed, 77 insertions(+), 5 deletions(-)

diff --git a/drivers/baseband/acc/meson.build b/drivers/baseband/acc/meson.build
index 27a654b501..84f4fea635 100644
--- a/drivers/baseband/acc/meson.build
+++ b/drivers/baseband/acc/meson.build
@@ -1,7 +1,28 @@
 # SPDX-License-Identifier: BSD-3-Clause
 # Copyright(c) 2020 Intel Corporation
 
-deps += ['bus_pci']
+# check for FlexRAN SDK libraries
+dep_dec5g = dependency('flexran_sdk_ldpc_decoder_5gnr', required: false)
+
+if dep_dec5g.found()
+    ext_deps += cc.find_library('stdc++', required: true)
+    ext_deps += cc.find_library('irc', required: true)
+    ext_deps += cc.find_library('imf', required: true)
+    ext_deps += cc.find_library('ipps', required: true)
+    ext_deps += cc.find_library('svml', required: true)
+    ext_deps += dep_dec5g
+    ext_deps += dependency('flexran_sdk_ldpc_encoder_5gnr', required: true)
+    ext_deps += dependency('flexran_sdk_LDPC_ratematch_5gnr', required: true)
+    ext_deps += dependency('flexran_sdk_rate_dematching_5gnr', required: true)
+    ext_deps += dependency('flexran_sdk_turbo', required: true)
+    ext_deps += dependency('flexran_sdk_crc', required: true)
+    ext_deps += dependency('flexran_sdk_rate_matching', required: true)
+    ext_deps += dependency('flexran_sdk_common', required: true)
+    cflags += ['-DRTE_BBDEV_SDK_AVX2']
+    cflags += ['-DRTE_BBDEV_SDK_AVX512']
+endif
+
+deps += ['bbdev', 'bus_pci']
 
 sources = files('rte_acc100_pmd.c', 'rte_vrb_pmd.c')
 
diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c
index 8a9c296b01..292537e24d 100644
--- a/drivers/baseband/acc/rte_acc100_pmd.c
+++ b/drivers/baseband/acc/rte_acc100_pmd.c
@@ -22,6 +22,10 @@
 #include "acc101_pmd.h"
 #include "vrb_cfg.h"
 
+#ifdef RTE_BBDEV_SDK_AVX512
+#include <phy_rate_dematching_5gnr.h>
+#endif
+
 #ifdef RTE_LIBRTE_BBDEV_DEBUG
 RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG);
 #else
@@ -3058,7 +3062,8 @@ derm_workaround_recommended(struct rte_bbdev_op_ldpc_dec *ldpc_dec, struct acc_q
 /** Enqueue one decode operations for ACC100 device in CB mode */
 static inline int
 enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op,
-		uint16_t total_enqueued_cbs, bool same_op)
+		uint16_t total_enqueued_cbs, bool same_op,
+		struct rte_bbdev_queue_data *q_data)
 {
 	int ret;
 	if (unlikely(check_bit(op->ldpc_dec.op_flags,
@@ -3113,8 +3118,54 @@ enqueue_ldpc_dec_one_op_cb(struct acc_queue *q, struct rte_bbdev_dec_op *op,
 		struct acc_fcw_ld *fcw;
 		uint32_t seg_total_left;
 
-		if (derm_workaround_recommended(&op->ldpc_dec, q))
-			rte_bbdev_log(INFO, "Corner case may require deRM pre-processing");
+		if (derm_workaround_recommended(&op->ldpc_dec, q)) {
+			#ifdef RTE_BBDEV_SDK_AVX512
+			struct rte_bbdev_op_ldpc_dec *dec = &op->ldpc_dec;
+			struct bblib_rate_dematching_5gnr_request derm_req;
+			struct bblib_rate_dematching_5gnr_response derm_resp;
+			uint8_t *in;
+
+			/* Checking input size is matching with E */
+			if (dec->input.data->data_len < (dec->cb_params.e % 65536)) {
+				rte_bbdev_log(ERR, "deRM: Input size mismatch");
+				return -EFAULT;
+			}
+			/* Run first deRM processing in SW */
+			in = rte_pktmbuf_mtod_offset(dec->input.data, uint8_t *, in_offset);
+			derm_req.p_in = (int8_t *) in;
+			derm_req.p_harq = (int8_t *) q->derm_buffer;
+			derm_req.base_graph = dec->basegraph;
+			derm_req.zc = dec->z_c;
+			derm_req.ncb = dec->n_cb;
+			derm_req.e = dec->cb_params.e;
+			if (derm_req.e > ACC_MAX_E) {
+				rte_bbdev_log(WARNING,
+						"deRM: E %d > %d max",
+						derm_req.e, ACC_MAX_E);
+				derm_req.e = ACC_MAX_E;
+			}
+			derm_req.k0 = 0; /* Actual output from SDK */
+			derm_req.isretx = false;
+			derm_req.rvid = dec->rv_index;
+			derm_req.modulation_order = dec->q_m;
+			derm_req.start_null_index =
+					(dec->basegraph == 1 ? 22 : 10)
+					* dec->z_c - 2 * dec->z_c
+					- dec->n_filler;
+			derm_req.num_of_null = dec->n_filler;
+			bblib_rate_dematching_5gnr(&derm_req, &derm_resp);
+			/* Force back the HW DeRM */
+			dec->q_m = 1;
+			dec->cb_params.e = dec->n_cb - dec->n_filler;
+			dec->rv_index = 0;
+			rte_memcpy(in, q->derm_buffer, dec->cb_params.e);
+			/* Capture counter when pre-processing is used */
+			q_data->queue_stats.enqueue_warn_count++;
+			#else
+			RTE_SET_USED(q_data);
+			rte_bbdev_log(INFO, "Corner case may require deRM pre-processing in SDK");
+			#endif
+		}
 
 		fcw = &desc->req.fcw_ld;
 		q->d->fcw_ld_fill(op, fcw, harq_layout);
@@ -3647,7 +3698,7 @@ acc100_enqueue_ldpc_dec_cb(struct rte_bbdev_queue_data *q_data,
 			ops[i]->ldpc_dec.n_cb, ops[i]->ldpc_dec.q_m,
 			ops[i]->ldpc_dec.n_filler, ops[i]->ldpc_dec.cb_params.e,
 			same_op);
-		ret = enqueue_ldpc_dec_one_op_cb(q, ops[i], i, same_op);
+		ret = enqueue_ldpc_dec_one_op_cb(q, ops[i], i, same_op, q_data);
 		if (ret < 0) {
 			acc_enqueue_invalid(q_data);
 			break;
-- 
2.34.1

[PATCH v2 2/2] doc: update FlexRAN SDK links

[Nicolas Chautru]

From: Hernan Vargas <hernan.vargas@intel.com>

Update FlexRAN SDK module link to use FEC_SDK_23.07.
Update compiler links to use ICX.
Update build SDK build instructions.

Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
---
 doc/guides/bbdevs/turbo_sw.rst | 53 +++++++++++++++++++---------------
 1 file changed, 30 insertions(+), 23 deletions(-)

diff --git a/doc/guides/bbdevs/turbo_sw.rst b/doc/guides/bbdevs/turbo_sw.rst
index 1056e7a47a..9445cf1327 100644
--- a/doc/guides/bbdevs/turbo_sw.rst
+++ b/doc/guides/bbdevs/turbo_sw.rst
@@ -67,11 +67,13 @@ FlexRAN SDK Download
 As an option it is possible to link this driver with FleXRAN SDK libraries
 which can enable real time signal processing using AVX instructions.
 
-These libraries are available through this `link <https://software.intel.com/en-us/articles/flexran-lte-and-5g-nr-fec-software-development-kit-modules>`_.
+These libraries are available through this `link <https://github.com/intel/FlexRAN-FEC-SDK-Modules/tree/Branch_FEC_SDK_23.07>`_.
 
 After download is complete, the user needs to unpack and compile on their
 system before building DPDK.
 
+To get the FlexRAN FEC SDK User manual extract this `doxygen <https://github.com/intel/FlexRAN-FEC-SDK-Modules/blob/Branch_FEC_SDK_23.07/doc/doxygen/html.zip>`_.
+
 The following table maps DPDK versions with past FlexRAN SDK releases:
 
 .. _table_flexran_releases:
@@ -83,6 +85,7 @@ The following table maps DPDK versions with past FlexRAN SDK releases:
    =====================  ============================
    19.08 to 22.07         19.04
    22.11+                 22.11
+   23.11+                 FEC_SDK_23.07
    =====================  ============================
 
 FlexRAN SDK Installation
@@ -91,31 +94,34 @@ FlexRAN SDK Installation
 Note that the installation of these libraries is optional.
 
 The following are pre-requisites for building FlexRAN SDK Libraries:
- (a) An AVX2 or AVX512 supporting machine
- (b) CentOS Linux release 7.2.1511 (Core) operating system is advised
- (c) Intel ICC 18.0.1 20171018 compiler or more recent and related libraries
-     ICC is `available with a free community license <https://software.intel.com/en-us/system-studio/choose-download#technical>`_.
+ (a) An AVX512 supporting machine.
+ (b) Ubuntu Linux release 22.04 operating system is advised.
+ (c) Intel ICX 2023.0.0 compiler or more recent and related libraries.
+     ICX is available `here <https://docs.o-ran-sc.org/projects/o-ran-sc-o-du-phy/en/latest/build_prerequisite.html#download-and-install-oneapi>`_.
+ (d) `FlexRAN SDK Modules <https://github.com/intel/FlexRAN-FEC-SDK-Modules/tree/Branch_FEC_SDK_23.07>`_.
+ (e) CMake 3.9.2 (Minimum 2.8.12)
+ (f) Google Test 1.7.0 (Required to run the verification and compute performance tests)
+ (g) Math Kernel Library 18.0 (Required by some functions in SDK)
 
 The following instructions should be followed in this exact order:
 
-#. Set the environment variables:
+#. Clone the SDK (Folder name needs to end in 'sdk')
 
     .. code-block:: console
 
-        source <path-to-icc-compiler-install-folder>/linux/bin/compilervars.sh intel64 -platform linux
+        git clone -b Branch_FEC_SDK_23.07 https://github.com/intel/FlexRAN-FEC-SDK-Modules.git flexran_sdk
 
-#. Run the SDK extractor script and accept the license:
+#. Set the environment variables:
 
     .. code-block:: console
 
-        cd <path-to-workspace>
-        ./FlexRAN-FEC-SDK-19-04.sh
+        source <path-to-workspace>/export_settings.sh -o -avx512
 
 #. Generate makefiles based on system configuration:
 
     .. code-block:: console
 
-        cd <path-to-workspace>/FlexRAN-FEC-SDK-19-04/sdk/
+        cd <path-to-workspace>
         ./create-makefiles-linux.sh
 
 #. A build folder is generated in this form ``build-<ISA>-<CC>``, enter that
@@ -123,11 +129,11 @@ The following instructions should be followed in this exact order:
 
     .. code-block:: console
 
-        cd build-avx512-icc/
-        make && make install
+        cd <path-to-workspace>/build-${WIRELESS_SDK_TARGET_ISA}-${WIRELESS_SDK_TOOLCHAIN}/
+        make -j$(nproc) && make install
 
-Initialization
---------------
+DPDK Initialization
+~~~~~~~~~~~~~~~~~~~
 
 In order to enable this virtual bbdev PMD, the user may:
 
@@ -142,18 +148,20 @@ In order to enable this virtual bbdev PMD, the user may:
 
 Example:
 
-.. code-block:: console
+    .. code-block:: console
 
-    export FLEXRAN_SDK=<path-to-workspace>/FlexRAN-FEC-SDK-19-04/sdk/build-avx2-icc/install
-    export DIR_WIRELESS_SDK=<path-to-workspace>/FlexRAN-FEC-SDK-19-04/sdk/build-avx2-icc/
-    export PKG_CONFIG_PATH=$DIR_WIRELESS_SDK/pkgcfg:$PKG_CONFIG_PATH
-    cd build
-    meson configure
+        export FLEXRAN_SDK=<path-to-workspace>/build-${WIRELESS_SDK_TARGET_ISA}-${WIRELESS_SDK_TOOLCHAIN}/install
+        export DIR_WIRELESS_SDK=<path-to-workspace>/build-${WIRELESS_SDK_TARGET_ISA}-${WIRELESS_SDK_TOOLCHAIN}
+        export PKG_CONFIG_PATH=${DIR_WIRELESS_SDK}/pkgcfg:${PKG_CONFIG_PATH}
+        cd build
+        meson configure
 
 * For AVX512 machines with SDK libraries installed then both 4G and 5G can be enabled for full real time FEC capability.
   For AVX2 machines it is possible to only enable the 4G libraries and the PMD capabilities will be limited to 4G FEC.
   If no library is present then the PMD will still build but its capabilities will be limited accordingly.
 
+SW Turbo PMD Usage
+~~~~~~~~~~~~~~~~~~
 
 To use the PMD in an application, user must:
 
@@ -169,9 +177,8 @@ The following parameters (all optional) can be provided in the previous two call
 * ``max_nb_queues``: Specify the maximum number of queues in the device (default is ``RTE_MAX_LCORE``).
 
 Example:
-~~~~~~~~
 
-.. code-block:: console
+  .. code-block:: console
 
     ./test-bbdev.py -e="--vdev=baseband_turbo_sw,socket_id=0,max_nb_queues=8" \
     -c validation -v ./turbo_*_default.data
-- 
2.34.1